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data sheet c-5 network processor silicon revision d0 C5NPD0-DS/d rev 04 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
data sheet c-5 network processor silicon revision d0 C5NPD0-DS/d rev 04 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
copyright ? 2002 motorola ? , inc. all rights reserved. no part of this documentation may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from motorola. motorola reserves the right to revise this documentation and to make changes in content from time to time without obligation on the part of motorola to provide notification of such revision or change. motorola provides this documentation without warranty, term, or condition of any kind, either implied or expressed, including, but not limited to, the implied warranties, terms or conditions of merchantability, satisfactory quality, and fitness for a particular purpose. motorola may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. c-3e, c-5, c-5e, c-port, c-ware, q-3, and q-5 are trademarks of c-port, a motorola company. motorola and the stylized motorola logo are registered in the us patent & trademark office. all other product or service names are the property of their respective owners. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola general business information C5NPD0-DS/d rev 04 C5NPD0-DS/d rev 04 contents about this guide data sheet description and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 using c-port electronic documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 guide conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 related product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 c hapter 1 functional description feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 channel processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 executive processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 system interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 fabric processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 buffer management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table lookup unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 external mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 queue management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 c hapter 2 signal descriptions signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 pin descriptions grouped by function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 lvttl and lvpecl specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 cp interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ds1/t1 framer interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10/100 ethernet (rmii) configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 gigabit ethernet (gmii) configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 gigabit ethernet and fibre channel tbi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 sonet oc-3 transceiver interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6 contents C5NPD0-DS/d rev 04 motorola general business information sonet oc-12 transceiver interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 executive processor system interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 pci signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 serial interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 prom interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 general system interface signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 fabric processor interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 bmu sdram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 tlu sram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 qmu sram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 power supply signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 test signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 no connection pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 signals grouped by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 jtag support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 jtag data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 boundary scan cell types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 idcode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 jtag instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 boundary scan description language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 c hapter 3 electrical specifications absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 power and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ac timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 clock timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 cp timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ds1/ds3 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10/100 ethernet timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 gigabit gmii ethernet, tbi and mii interface timing specifications . . . . . . . . . . . . . . . . . . 77 oc-3 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 oc-12 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 executive processor timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
contents 7 motorola general business information C5NPD0-DS/d rev 04 pci timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 mdio serial interface timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 low speed serial interface timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 prom interface timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 fabric processor timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 bmu timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 tlu timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 qmu timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 c hapter 4 mechanical specifications package views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 package measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 marking codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 typical reflow profile for the c-5 switch module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8 contents C5NPD0-DS/d rev 04 motorola general business information f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola general business information C5NPD0-DS/d rev 04 C5NPD0-DS/d rev 04 list of figures 1 c-5 network processor block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2 pin locations (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3 gmii/tbi transmit and receive pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4 prom interface diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5 prom interface timing outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6 power and ground connections (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7 observe-only cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8 cell design that can be used for both input and output pins . . . . . . . . . . . . . . . . . . . . . . . 64 9 bringup clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10 thermal performance for c-5 network processor heat sink (see step 2 above). . . . . . . . . . 72 11 test loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12 system clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 13 ds1/ds3 ethernet timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 14 10/100 ethernet timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 15 gigabit ethernet and tbi interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 16 oc-3 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 17 oc-12 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 18 pci timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 19 mdio serial interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 20 low speed serial interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 21 prom interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 22 fabric processor timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 23 bmu timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 24 tlu timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 25 qmu timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 26 c-5 network processor bga package side view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 27 c-5 network processor bga package (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10 C5NPD0-DS/d rev 04 motorola general business information f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola general business information C5NPD0-DS/d rev 04 C5NPD0-DS/d rev 04 list of tables list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1 navigating within a c-port electronic document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 c-5 network processor data sheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 c-port silicon documentation set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 tlu sram configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 clock and reference signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 cp physical interface signals and pins (grouped by clusters) . . . . . . . . . . . . . . . . . . . . . . . 31 7 ds1/t1 framer interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 10/100 ethernet signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 transmit and receive pin combinations for gigabit ethernet and fibre channel . . . . . . . . . 33 10 gigabit ethernet (gmii/mii) signals one cluster example. . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11 gigabit ethernet and fibre channel tbi signals example . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12 oc-3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 13 oc-12 signals example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 14 pci signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 15 serial port signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 16 prom interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 17 general system interface signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 18 fabric interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 19 utopia1*, 2, 3 atm mode, c-5 network processor to fabric interface pin mapping . . . . . 45 20 utopia1*, 2, 3 phy mode, c-5 network processor to fabric interface pin mapping . . . . . . 45 21 prizma mode, c-5 network processor to fabric interface pin mapping . . . . . . . . . . . . . . . 46 22 power x mode, c-5 network processor to fabric interface pin mapping . . . . . . . . . . . . . . . 47 23 bmu sdram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 24 tlu sram interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 25 memory bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 26 qmu sram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 27 power supply signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 28 miscellaneous test signals for jtag, scan, and internal test routines . . . . . . . . . . . . . 53 29 no connection pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
12 C5NPD0-DS/d rev 04 motorola general business information 30 signals listed by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 31 jtag internal register descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 32 jtag identification code and its sub-components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 33 instruction register instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 34 c-5 network processor absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 35 c-5 network processor recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . 68 36 c-5 network processor dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 37 c-5 network processor capacitance data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 38 c-5 network processor power and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 70 39 system clock timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 40 ds1/ds3 ethernet timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 41 10/100 ethernet timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 42 gigabit gmii/mii ethernet interface timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 43 gigabit tbi interface timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 44 oc-3 timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 45 oc-12 timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 46 pci timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 47 mdio serial interface timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 48 low speed serial interface timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 49 prom interface timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 50 fabric processor timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 51 bmu timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 52 signal groups in bmu timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 53 tlu timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 54 signal groups in tlu timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 55 qmu timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 56 signal groups in qmu timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 57 package measurements (reference figure 26 and figure 27 for symbols) . . . . . . . . . . . . . 95 58 c-5 network processor marking codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola general business information C5NPD0-DS/d rev 04 C5NPD0-DS/d rev 04 about this guide data sheet description and organization this data sheet describes the c-5 network processor, version d0. it provides hardware layout specifications including pinouts, memory configuration guidelines, timing diagrams, power and power sequencing guidelines, thermal design guidelines, and mechanical specifications. the data sheet is divided into the following topics: ? functional description signal descriptions electrical specifications mechanical specifications using c-port electronic documents c-port electronic documents are provided as pdf files. open and view them using the adobe? acrobat? reader application, verion 3.0 or later. if necessary, download the acrobat reader from the adobe systems, inc. web site: http://www.adobe.com/prodindex/acrobat/readstep.html each provided pdf file offers several ways for moving among the document?s pages, as follows: to move quickly from section to section within the document, use the acrobat bookmarks that appear on the left side of the acrobat reader window. the bookmarks provide an expandable ? outline ? view of the document ? s contents. to display the document ? s acrobat bookmarks, press the ? display both bookmarks and page ? button on the acrobat reader tool bar. to move to the referenced page of an entry in the document ? s contents or index, click on the entry itself, each of which is ? hot linked. ? to follow a cross-reference to a heading, figure, or table, click the blue text. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14 C5NPD0-DS/d rev 04 motorola general business information to move to the beginning or end of the document, to move page by page within the document, or to navigate among the pages you displayed by clicking on hyperlinks, use the acrobat reader navigation buttons shown in this figure: table 1 summarizes how to navigate within a c-port electronic document. guide conventions the following visual elements are used throughout this guide, where applicable: this icon and text designates information of special note. warning: this icon and text indicate a potentially dangerous procedure. instructions contained in the warnings must be followed. table 1 navigating within a c-port electronic document to navigate this way click this move from section to section within the document. a bookmark on the left side of the acrobat reader window move to an entry in the document ? s contents or index. the entry itself follow a cross-reference (highlighted in blue text). the cross-reference text move page by page. the appropriate acrobat reader navigation buttons move to the beginning or end of the document. the appropriate acrobat reader navigation buttons move backward or forward among a series of hyperlinks you have selected. the appropriate acrobat reader navigation buttons beginning of document end of document next page previous page previous or next hyperlink f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
revision history 15 motorola general business information C5NPD0-DS/d rev 04 warning: this icon and text indicate a procedure where the reader must take precautions regarding laser light. this icon and text indicate the possibility of electro-static discharge (esd) in a procedure that requires the reader to take the proper esd precautions. revision history table 2 shows the revision history for this data sheet, providing a description of the changes. table 2 c-5 network processor data sheet revision history revision date change page no. march 10, 2000 first printing for the c-5 np. june 12, 2000 chapter 2 contains the following revisions: ? lvttl and lvpecl specifications have been added. several of the tables listing pin configurations have had their descriptions updated. check each application ? s configuration table as required. cpn3+1 is rclkn (5/25/00), not nc (3/10/00) mechanism for eprom signaling has changed. xpuhot functionality is clarified qcpa is a nc (5/25/00), not address parity (3/10/00) the power and ground connections illustration has been updated. chapter 3 contains the following revisions: many values listed in individual timing diagrams and specification tables have updated or corrected. check each specification table as required. low speed serial interface timing specifications have been added. prom i/f timing specifications are changed 17 18 - 39 25 31 31 36 38 61 - 78 71 72 june 14, 2000 qmu timing specification for tqdo has been changed from 2.2 to 1.5. 77 july 17, 2000 updated bmu section to reflect change to external pipeline architecture, single data rate synchronous dram. 12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16 C5NPD0-DS/d rev 04 motorola general business information august 8, 2000 operating temperatiure range added. power sequencing diagram updated. bmu timing diagram updated. tlu timing diagram updated. qmu timing diagram updated. 54 56 75 77 78 march 26, 2001 chapter 1 contains the following revisions: fabric processor interface frequency changed from 100 mhz to 110 mhz thruoughout. tlu interface memory was incorrectly noted at 64 mbytes. changed to 32 mbytes. the maximum amount of memory supported by the tlu is 32mbytes in four banks. chapter 2 contains the following revisions: buffer management unit (bmu) has 161 pins added figure 5. prom interface timing outline added figure 7. observe-only cell added figure 8. cell design that can be used for both input and output pins prom interface timing outline added. numerous changes in tables 17, 18 and 19 data lines incorrectly noted at 128. the useful configuration is 139 data lines and all 12 address lines. the tlu sram interface was incorrectly noted at 64 mbytes. changed to 32 mbytes. chapter 3 contains the following revisions: table 40, gigabit ethernet (tbi) timing description, tcgr min value of -1.0 removed. figure 16, oc 12 clock duty cycle was added tc12d added to table 42 figure 17, executive processor pci timing diagram pgntx is only an input. pgntx output removed. tpgo, tpgz, tpgv removed from table 43. chapter 4 contains the following revisions: mechanical specs changed. thru-out 18 19 21 37 57 36 39, 40 41 42 71 73 73 74 75 table 2 c-5 network processor data sheet revision history revision date change page no. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
related product documentation 17 motorola general business information C5NPD0-DS/d rev 04 related product documentation the following table lists the c-5 and cst documentation set. find the latest editions of these documents for your installed cst version in the support section of the c-port corporation web site: october 1, 2001 chapter 2 contains the following revisions: lvttl and lvpecl conform to the jedec jesd8-bspecification table 3 changed to note lvpecl differential signal table 10 lvpecl change table 11 cp n _6 and cp n+1 _6 changed table 21 changed to reflect pin g14 used for signal mdqml table 27 changed to reflect total number of nc pins for d0 table 28 changed to reflect g14 receiving signal mdqml c-port web site support address added chapter 3 contains the following revisions table 32 storage / max junction temperatures added table 34 lvpecl high and low voltage min / max added table 36 power dissipation, p d min, max, typical changed chapter 4 contains the following revisions added ? marking codes ? added ? reflow ? profile 23 23 31 31 32 42 48 61 63 65 67 91 91 september 9, 2002 chapter 1 contains the following revisions: table 4 contain revised tlu sram configuration specifications chapter 2 contains the following revisions: tlu sram interface signals: table 24 and table 25 changed to reflect memory bank selection chapter 3 contains the following revisions: table 50 , table 51 and table 53 contain revised timing specifications 25 49 87 thru 90 table 2 c-5 network processor data sheet revision history revision date change page no. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18 C5NPD0-DS/d rev 04 motorola general business information table 3 c-port silicon documentation set document subject document name purpose document id processor information c-5 network processor architecture guide describes the full architecture of the c-5 network processor. c5nparch-rm/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola general business information C5NPD0-DS/d rev 04 C5NPD0-DS/d rev 04 chapter 1 functional description feature list complete programmability programmability at all levels of the protocol stack: layers 2-7 examples of c-5 enabled systems: ? multiservice access platforms (msaps) ? optical edge switch/routers ? ip gigabit/terabit routers ? wan customer premises equipment (cpe) ? load balancing web server switches simple programming model c/c++ programmable standard instruction set standard applications programming interface (c-ware api tm ) comprehensive c-ware tm software toolset (easy to program, debug, and tune applications) maximum system flexibility software implementation of functions from physical interfaces through switching fabric support reprogram to support new functionality and ratified standards, improving your time-in -market tm metric deliver new services to market through simple software upgrades ? no forklift massive processing power operating frequencies: 166mhz, 200mhz, and 233mhz 5gbps of bandwidth (for non-blocking throughput) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20 chapter 1: functional description C5NPD0-DS/d rev 04 motorola general business information more than 3,000mips of computing power (for adding services throughout the protocol stack) up to 15 million packets per second transmitted at wire speed 17 programmable risc cores (for cell/packet forwarding) 32 programmable serial data processors (for processing bit streams) up to 133 million table lookups per second three internal buses for 60gb of aggregate bandwidth high functional integration 838 pin ball grid array (bga) package 16 channel processors including: ? embedded oc-3c, oc-12, oc-12c sonet framers ? programmable mac interface ? risc cores ? programmable pin phy interfaces embedded coprocessors for table lookup (classification), buffer memory (payload control), and queue management (cos/qos implementation) dedicated fabric processor and port embedded risc executive processor integrated 32bit/66mhz pci bus stable programming interfaces supports generic communications programming interfaces to simplify programming and allow future reuse of code across generations of the processor network processing forum (npf), (formerly cpix), charter member third-party support support for virtually any third-party protocol stack, phy or fabric interface, and industry standard tools smart networks alliance program ensures a wide range of verified solutions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
block diagram 21 motorola general business information C5NPD0-DS/d rev 04 block diagram the c-5 tm network processor, has an architecture specifically designed for networking applications. figure 1 shows a block diagram of the c-5 np, including its potential external interfaces. the following sections describe each component of the c-5 np. for more information about the architecture of the c-5 np, see the c-5 network processor architecture guide . figure 1 c-5 network processor block diagram the main components of the c-5 np are: channel processors executive processor fabric processor buffer management unit table lookup unit queue management unit phy phy phy phy phy phy phy phy buses (60gbps bandwidth) cluster cluster cp-1 cp-0 cp-2 cp-3 cp-12 cp-13 cp-14 cp-15 external host cpu (optional) oc-3 phy interface examples: oc-12 gigabit ethernet 10/100 ethernet external prom (optional) control logic (optional) fabric processor boundary buffer mgmt unit channel processors sdram c-5 np sram sram table lookup unit fabric processor executive processor queue mgmt unit pci serial prom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
22 chapter 1: functional description C5NPD0-DS/d rev 04 motorola general business information channel processors the c-5 np contains sixteen programmable channel processors (cps) that receive, process, and transmit network data. the number of cps per port is configurable, depending on the line interface. typically one cp is assigned to each port for medium bandwidth applications (fast ethernet to oc-3). multiple cps can be assigned to a port in a configuration called channel aggregation in high bandwidth applications (greater than oc-3). multiple logical ports can be assigned to a single cp, with the addition of an external multiplexor, for low bandwidth applications, such as ds1 to ds3. the c-5 np ? s architecture supports a variety of industry-standard serial and parallel protocols and individual port data rates including: 10mb ethernet (rmii) 100mb ethernet (rmii) 1gb ethernet (gmii and tbi) oc-3 oc-12 ds1/ds3, supported through the use of external framers/multiplexors the c-5 np?s programmability can also support a variety of special interfaces, such as various xdsl encapsulations and proprietary protocols. key components of each cp are a risc core (cprc) that orchestrates cell/packet processing and a set of microprogrammable, special-purpose processors, called serial data processors (sdps), that provide features such as ethernet mac and sonet framing, multichannel hdlc, and atm cell delineation. this means you usually only need to include phys to complete the system. executive processor the executive processor (xp) serves as a centralized computing resource for the c-5 np and manages the system interfaces. the xp performs conventional supervisory tasks in the c-5 np, including: reset and initialization of the c-5 np program loading and control of cps centralized exception handling f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
fabric processor 23 motorola general business information C5NPD0-DS/d rev 04 management of a host interface through the pci management of system interfaces (pci, serial bus, prom) system interfaces the system interfaces to the xp are: pci ? provides an industry standard 32bit 33/66mhz pci channel used for chip-level shared resources. the pci has both initiator and target capabilities. the pci interface is typically connected to a host processor. serial bus interface ? provides a general purpose bi-directional, two-wire serial bus and i/o port that allows the c-5 np to control external logic with either of two standard protocols: ? the mdio (high-speed) protocol : uses a 16bit data format with 10bits of addressing and supports transfers up to 25mhz. ? the low-speed protocol : uses an 8bit data format followed by an acknowledge bit and supports transfers up to 400kbps. software is used to select which protocol to use, by setting the appropriate bits in the serial bus configuration register. when a serial bus transfer is active, an external pin is driven by the c-5 np to indicate which protocol is being used (spld=0 indicates mdio protocol; spld=1 indicates low-speed protocol). both sida and sicl are bi-directional lines that are connected, via an external pull-up resistor, to a positive supply voltage. when the bus is free, both lines are high because of the pull-up resistor. the output stages of the devices connected to the bus must have either an open-drain or open-collector in order to perform the wired-and function required for its arbitration mechanism. prom interface ? allows the xp to boot from nonvolatile, flash memory. the prom interface is a low-speed, serial i/o port that runs at 1 / 2 to 1 / 16 the core clock rate. the maximum prom size is 8mbytes, and a 16bit wide configuration is required. external board logic is required to perform serial-to-parallel conversion for prom address outputs and parallel-to-serial conversion for prom data inputs. fabric processor the fabric processor (fp) acts as a high-speed network interface port with advanced functionality. it allows the c-5 np to interface to an application-specific switching solution internal to your design. the fp port supports the bidirectional transfer of packets, frames, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
24 chapter 1: functional description C5NPD0-DS/d rev 04 motorola general business information or cells from the c-5 np to a hardware interface that provides connectivity to other network processors or other similar line processing hardware. there are numerous parameters that can be configured within the fp to allow the interface to be adapted to different fabric protocols. the fp is utopia-1, 2 and utopia-3, ibm prizma, and powerx (csix-l0) compatible. the fp can be configured to run at any frequency up to 110mhz, and the receive and transmit data buses are 16 or 32 bits wide. this allows a wide range of supported bandwidths to and from the switching fabric, all the way up to 3200mbps full duplex bandwidth. buffer management unit the buffer management unit (bmu) interfaces the c-5 np to external pipeline architecture, single data rate synchronous dram. the external memory is partitioned and used as buffers for receiving and transmitting data between cps, the fp, and the xp. it is also used as second level storage in the xp memory hierarchy. the interface to an array of sdram chips is 139bits wide, composed of 128 data bits, two internal control bits, and nine secded (single error correction-double error detection) ecc (error correction code) bits. the interface is compliant with the pc100 standard and operates at up to 125mhz with 3.3v lvttl-compatible inputs and outputs. the refresh period, trcd, tcas, trp, tmrd, and trc are configurable via boot time configuration (see the c-5 network processor architecture guide for more details). the c-5 np uses auto-refresh mode and the interface, (which is not configurable), transfers four bits of data for each read and write using a sequential burst type. some of these parameters are programmed into the sdrams ? mode register and can be applied only once per power cycle. the ecc functionality can be enabled or disabled via configuration register writes. if needed, the interface can narrowed to 128bits by disabling ecc and providing board pull-ups for the two control bits and nine ecc bits. this is useful if dimms are used in the board design. if individual sdram parts are used, x16 and x32 are supported. the bmu supports sdram devices that use 12 address lines. internal address calculation paths limit the maximum memory size to 128mbytes. only one physical bank of sdram is supported. table lookup unit the table lookup unit (tlu) performs table lookups in external sram. it can also be used for statistics accumulation and retrieval and as general data storage. the tlu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
external mode 25 motorola general business information C5NPD0-DS/d rev 04 simultaneously supports multiple application-defined tables and multiple search strategies, such as those needed for routing, circuit switching, and qos lookup tasks. the c-5 np uses external 64bit wide zbt pipelined bursting static ram (sram) modules (at frequencies to 133mhz) for storage of its tables. these modules allow implementation of tables with 2 20 x 64bit entries at a cycle time of up to 7.5 nanoseconds using 4mbit sram technology. the maximum amount of memory supported by the tlu is 32mbytes in four banks. external mode there is support for external devices. refer to the c-5 archictecture guide . queue management unit the queue management unit (qmu) autonomously manages a number of application-defined descriptor queues. it handles inter-cp and inter-c-5 np descriptor flows by providing switching and buffering. it also performs descriptor replication for multicast applications. a number of queues can be assigned to each cprc for qos-based services. the qmu provides a queuing engine internal to the chip and uses external sram to store the descriptors. scheduling is done by the cps. the qmu supports up to 512 queues and 16, 384 descriptor buffers. a descriptor buffer holds an application-defined ? descriptor ? , which is a structure that defines the payload buffer handle and other attributes of the forwarded cell or packet. the qmu ? s external sram interface uses zbt synchronous srams organized in a single bank of up to 128k, 32bit words. this interface runs at half ( 1 / 2 ) the core clock frequency. table 4 tlu sram configurations sram technology* * for (n x 32) parts, divide total memory and number of parts by two. min table size (one bank) no. of parts maximum table size (four banks) no. of parts 1mbit (32k x 32) 256kbytes 2 1mbytes 8 2mbit (64k x 32) 512kbytes 2 2mbytes 8 4mbit (256k x 18) 2mbytes 4 8mbytes 16 8mbit (512k x 18 4mbytes 4 16mbytes 16 16mbit (1m x 18) 8mbytes 4 32mbytes 16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
26 chapter 1: functional description C5NPD0-DS/d rev 04 motorola general business information f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola general business information C5NPD0-DS/d rev 04 C5NPD0-DS/d rev 04 chapter 2 signal descriptions signal summary there are ten functional groupings of signals in the c-5 network processor: clock ? 11 pins channel processors (cp0 - cp15) ? 16x7 = 112 pins executive processor (xp) ? 57 pins ? pci interface ? 50 pins ? prom interface ? 4 pins ? serial bus interface ? 2 pins ? general system interface ? 1 pin fabric processor (fp) ? 80 pins buffer management unit (bmu) ? 161 pins table lookup unit (tlu) ? 100 pins queue management unit (qmu) ? 55 pins power ? 233 pins test ? 18 pins no connection (nc) ? 11 pins two of the sections (cps and fp) are configurable, depending on the type of device being implemented. pinout diagram the c-5 np contains 838 pins as shown in figure 2 . these pin numbers are referenced throughout the remaining chapter. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
28 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information figure 2 pin locations (bottom view) pin descriptions grouped by function the c-5 np pins are categorized in groups, reflecting interfaces to the chip: clock signals cp interface signals executive processor system interface signals 838 total pins c-5 network processor ac ab aa z y x w v u t s r q p o n m l k j i h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2 5 26 27 28 29 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pin descriptions grouped by function 29 motorola general business information C5NPD0-DS/d rev 04 fabric processor interface signals bmu sdram interface signals tlu sram interface signals qmu sram interface signals power supply signals test signals no connection pins lvttl and lvpecl specifications c-5 np pins are the following types: low voltage ttl-compatible (lvttl). the c-5 np ? s lvttl pins conform to the jedec jesd8-b specification. low voltage positive emitter coupled logic (lvpecl). the c-5 np ? s lvpecl pins conform to the jedec jesd8-2 specification. clock signals table 5 describes the c-5 np clock signals. table 5 clock and reference signals signal name pin # total type i/o signal description sclk* sclkx* h15 g15 1 1 lvpecl lvpecl i i core clock rate (differential) cclk0 k12 1 lvt tl i 1_544mhz_clk (t1) ? cclk1 j13 1 lvt tl i 2_048mhz_clk (e1) ? cclk2 j15 1 lvt tl i 34_368mhz_clk (e3) ? cclk3 i12 1 lvt tl i 44_736mhz_clk (t3) ? cclk4 i14 1 lvt tl i 50mhz_clk (100mbit ethernet) ? cclk5 h13 1 lvt tl i 106_25mhz_clk (fibre channel) ? cclk6 k14 1 lvt tl i 125mhz_clk (gigabit ethernet) ? cclk7 k16 1 lvt tl i 155_52mhz_clk (oc-3) ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
30 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information cp interface signals the c-5 np ? s 16 cps support various network physical interfaces, providing a serial interface to the phy layer. interfaces are configured via bits in the c-5 np register set. many interfaces are possible by programming the configuration registers. cps can be used individually or in a cluster (four cps) to implement the various interfaces. table 6 provides a quick reference of all the cp pins organized by clusters. there are seven physical i/o pins associated with each cp. all pins are capable of receiving data, with some configurable to be input clocks, output clocks, or data drivers. in addition, pairs of pins can be configured as differential pairs for lvpecl compatibility. in the case of rmii, oc-3, ds1, and ds3, the drivers and receivers at the pin are locally configured to match the relevant phy or framer chip. oc-12 uses the aggregation of four cps (one cluster), while gmii and ten bit interface (tbi) can use either eight cps (four for receive and four for transmit) or four cps that share the transmit and receive functions for non-wire speed applications. during cp aggregation, all 28 pins associated with a cluster are routed to all of the serial data processors (sdps) in that cluster. this allows round-robin usage of portions of the sdps, with each getting access to the necessary i/o pins. the signals for the following cp physical interfaces are included in this section: ds1/t1 framer interface configuration 10/100 ethernet (rmii) configuration gigabit ethernet (gmii) configuration cpref ? l13 1 lvpecl i reference total 11 * sclk and sclkx must not be ac-coupled. ? the frequencies specified for cclk0 - cclk7 allow full flexibility for the c-5 np. clock inputs associated with a specific protocol should be wired to ground when that protocol is not used by the c-5 np. it is also possible to use one or more cclk n inputs for other frequencies. contact your c-port representative for more information. ? if any of the cps are configured for lvpecl operation (oc3) using the pin mode registers, then cpref must be wired to an external reference, as specified in table 36 on page 68. if none of the cps are configured for lvpecl operation, then the cpref pin can be left unconnected. it is acceptable to tie the cpref pin high or low through a resistor, or into the specified reference, but this is not required. table 5 clock and reference signals (continued) signal name pin # total type i/o signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pin descriptions grouped by function 31 motorola general business information C5NPD0-DS/d rev 04 gigabit ethernet and fibre channel tbi configuration sonet oc-3 transceiver interface configuration sonet oc-12 transceiver interface configuration table 6 cp physical interface signals and pins (grouped by clusters) cp cluster 1 cp cluster 2 cp cluster 3 cp cluster 4 signal pin # signal pin # signal pin # signal pin # cp0_0 ac28 cp4_0 ab22 cp8_0 z29 cp12_0 y28 cp0_1 ac26 cp4_1 ab21 cp8_1 z28 cp12_1 y26 cp0_2 ac24 cp4_2 ab20 cp8_2 z27 cp12_2 y24 cp0_3 ac22 cp4_3 ab19 cp8_3 z26 cp12_3 y22 cp0_4 ac20 cp4_4 ab18 cp8_4 z25 cp12_4 y20 cp0_5 ac18 cp4_5 ab17 cp8_5 z24 cp12_5 y18 cp0_6 ac16 cp4_6 ab16 cp8_6 z23 cp12_6 y16 cp1_0 ac02 cp5_0 ab08 cp9_0 z01 cp13_0 y02 cp1_1 ac04 cp5_1 ab09 cp9_1 z02 cp13_1 y04 cp1_2 ac06 cp5_2 ab10 cp9_2 z03 cp13_2 y06 cp1_3 ac08 cp5_3 ab11 cp9_3 z04 cp13_3 y08 cp1_4 ac10 cp5_4 ab12 cp9_4 z05 cp13_4 y10 cp1_5 ac12 cp5_5 ab13 cp9_5 z06 cp13_5 y12 cp1_6 ac14 cp5_6 ab14 cp9_6 z07 cp13_6 y14 cp2_0 ab29 cp6_0 aa28 cp10_0 z22 cp14_0 x29 cp2_1 ab28 cp6_1 aa26 cp10_1 z21 cp14_1 x28 cp2_2 ab27 cp6_2 aa24 cp10_2 z20 cp14_2 x27 cp2_3 ab26 cp6_3 aa22 cp10_3 z19 cp14_3 x26 cp2_4 ab25 cp6_4 aa20 cp10_4 z18 cp14_4 x25 cp2_5 ab24 cp6_5 aa18 cp10_5 z17 cp14_5 x24 cp2_6 ab23 cp6_6 aa16 cp10_6 z16 cp14_6 x23 cp3_0 ab01 cp7_0 aa02 cp11_0 z08 cp15_0 x01 cp3_1 ab02 cp7_1 aa04 cp11_1 z09 cp15_1 x02 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
32 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information ds1/t1 framer interface configuration table 7 describes the serial framer interface signals. for each cp (0-15), you can implement one serial framer interface. 10/100 ethernet (rmii) configuration table 8 describes the 10/100base-t ethernet reduced media independent interface (rmii) signals. for each cp (0-15), you can implement one 10/100 ethernet interface. cp3_2 ab03 cp7_2 aa06 cp11_2 z10 cp15_2 x03 cp3_3 ab04 cp7_3 aa08 cp11_3 z11 cp15_3 x04 cp3_4 ab05 cp7_4 aa10 cp11_4 z12 cp15_4 x05 cp3_5 ab06 cp7_5 aa12 cp11_5 z13 cp15_5 x06 cp3_6 ab07 cp7_6 aa14 cp11_6 z14 cp15_6 x07 table 6 cp physical interface signals and pins (grouped by clusters) (continued) cp cluster 1 cp cluster 2 cp cluster 3 cp cluster 4 signal pin # signal pin # signal pin # signal pin # table 7 ds1/t1 framer interface signals signal name* pin #? total type i/o label signal description cp n _0 table 6 1 lvt tl o tclk transmit clock (1.544mhz) cp n _1 table 6 1 lvt tl i rclk receive clock (1.544mhz) cp n _2 table 6 1 lvt tl o tdata transmit data cp n _3 table 6 1 lvt tl o tframe transmit frame synchronization cp n _4 table 6 1 lvt tl i rdata receive data cp n _5 table 6 1 lvt tl i rframe receive frame synchronization cp n _6 table 6 1 nc nc nc nc total pins 7 * n can be from 0 to 15. see table 6 . ? reference table 6 for pin numbers for the actual cluster(s) you are configuring. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pin descriptions grouped by function 33 motorola general business information C5NPD0-DS/d rev 04 gigabit ethernet (gmii) configuration gigabit ethernet media independent interface (gmii) is configured in one of two ways: 1 use one cp cluster when density is more important than wire-speed performance because you can then implement up to four gigabit ethernet ports per c-5 np. 2 use two cp clusters for wire-speed performance and additional processing power. you can implement up to two gigabit ethernet ports per c-5 np. table 9 lists the possible cp cluster combinations you can use and figure 3 shows receive and transmit pin configurations by cluster. table 10 lists the signals and pinouts for gigabit ethernet (gmii). table 8 10/100 ethernet signals signal name* pin # total type i/o label signal description cp n _0 table 6 1 lvt tl o ref_clk transmit and receive clock (50mhz) cp n _1 table 6 1 lvt tl i crs_dv carrier sense (crs)/ receive data valid (rx_dv). crs indicates that traffic is on the link, and is asserted if the signal is a 1 or an alternating 1010... rx_dv indicates that a receive frame is in progress and the data present on the rxd pins is valid. it is asserted if this signal is a 1 for more than one cycle. cp n _2 table 6 1 lvt tl o txd(0) transmit data 0 (first on wire) cp n _3 table 6 1 lvt tl o txd(1) transmit data 1 (second on wire) cp n _4 table 6 1 lvt tl i rxd(0) receive data 0 (first on wire) cp n _5 table 6 1 lvt tl i rxd(1) receive data 1 (second on wire) cp n _6 table 6 1 lvt tl o tx_en transmit enable. when asserted, the data on txd is encoded and transmitted on the twisted pair cable. total pins 7 * n can be from 0 to 15. see table 6 . table 9 transmit and receive pin combinations for gigabit ethernet and fibre channel cluster single cluster mode (tbi or gmii) two cluster mode (gmii)* * the two cluster mode column lists typical configurations. any cluster can be set up to either receive or transmit. so you could configure a dual cluster mode where cluster 0 receives and cluster 3 transmits. 0 port 1 tx and rx port 1 tx 1 port 2 tx and rx port 1 rx 2 port 3 tx and rx port 2 tx 3 port 4 tx and rx port 2 rx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
34 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information figure 3 gmii/tbi transmit and receive pin configurations the unused cp pins in the two cluster configurations should be wired to ground using a resistor. cluster 0 cluster 1 cluster 2 cluster 3 port 1 port 2 port 3 port 4 } } } } tx tx tx tx rx rx rx rx single cluster mode pin configuration port 1 port 2 } tx tx tx tx rx rx rx rx two cluster mode pin configuration nc nc nc nc } nc = not connected cluster 0 cluster 1 cluster 2 cluster 3 table 10 gigabit ethernet (gmii/mii) signals one cluster example signal name* pin # ? total type i/o label signal description cp n _0 table 6 1 lvt tl o t_clk gmii transmit clock (125mhz). this clock is used to synchronize the transmit data. cp n _1 table 6 1 lvt tl i tclki mii transmit clock. transmit data aligned to this clock input from phy in mii mode. 25 mhz in 100baset, 2.5 in mhz in 10baset cp n _2 table 6 1 lvt tl o txd(0) transmit data (byte-wide data, least significant bit) cp n _3 table 6 1 lvt tl o txd(1) transmit data cp n _4 table 6 1 lvt tl o txd(2) transmit data cp n _5 table 6 1 lvt tl o txd(3) transmit data cp n _6 table 6 1 lvt tl o tx_en transmit enable. when asserted, the data on txd is encoded and transmitted on the twisted pair cable. cp n+1 _0 table 6 1 nc nc nc nc cp n+1 _1 table 6 1 lvt tl i col collision. asserted when both rx_dv and tx_en are valid during half duplex operation. cp n+1 _2 table 6 1 lvt tl o txd(4) transmit data cp n+1 _3 table 6 1 lvt tl o txd(5) transmit data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pin descriptions grouped by function 35 motorola general business information C5NPD0-DS/d rev 04 gigabit ethernet and fibre channel tbi configuration 1000base-t gigabit ethernet and fibre channel tbi is implemented in much the same way as gigabit ethernet (gmii). table 9 shows the possible cp pin combinations you can cp n+1 _4 table 6 1 lvt tl o txd(6) transmit data cp n+1 _5 table 6 1 lvt tl o txd(7) transmit data (byte-wide receive data, most significant bit) cp n+1 _6 table 6 1 lvt tl o tx_er transmit error. asserting tx_er when tx_en is a 1 causes transmission of the designated ? bad code ? in lieu of the normal encoded data on the twisted pair data. cp n+2 _0 table 6 1 nc nc nc cp n+2 _1 table 6 1 lvt tl i rclk receive clock (125mhz) cp n+2 _2 table 6 1 lvt tl i rxd(0) receive data (byte-wide receive data, least significant bit) cp n+2 _3 table 6 1 lvt tl i rxd(1) receive data cp n+2 _4 table 6 1 lvt tl i rxd(2) receive data cp n+2 _5 table 6 1 lvt tl i rxd(3) receive data cp n+2 _6 table 6 1 lvt tl i rx_dv receive data valid. indicates that there is a receive frame in progress and that the data present on the rxd signals is valid. cp n+3 _0 table 6 1 nc nc nc nc cp n+3 _1 table 6 1 lvt tl i crs carrier sense. indicates traffic is on the link. crs is asserted when a non-idle condition is detected on the receive data stream. crs is deasserted when an end of frame or idle condition is detected. cp n+3 _2 table 6 1 lvt tl i rxd(4) receive data cp n+3 _3 table 6 1 lvt tl i rxd(5) receive data cp n+3 _4 table 6 1 lvt tl i rxd(6) receive data cp n+3 _5 table 6 1 lvt tl i rxd(7) receive data (most significant bit) cp n+3 _6 table 6 1 lvt tl i rx_er receive error detected. indicates that there has been an error received in the receive frame. total pins 28 * n can be 0, 4, 8, or 12. ? reference table 6 for pin numbers for the actual cluster(s) you are configuring. table 10 gigabit ethernet (gmii/mii) signals one cluster example (continued) signal name* pin # ? total type i/o label signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
36 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information use and figure 3 shows receive and transmit pin configurations by cluster. table 11 shows the signals and pinouts for a single cluster for gigabit ethernet and fibre channel tbi. the unused pins for the two cluster configurations should be wired down using a resistor. table 11 gigabit ethernet and fibre channel tbi signals example signal name* pin # ? total type i/o label signal description cp n _0 table 6 1 lvt tl o tclk transmit clock (125mhz). this clock is used to synchronize the transmit data. cp n _1 table 6 1 nc nc nc nc cp n _2 table 6 1 lvt tl o txd(9) transmit data (ten bits wide, last on wire) cp n _3 table 6 1 lvt tl o txd(8) transmit data cp n _4 table 6 1 lvt tl o txd(7) transmit data cp n _5 table 6 1 lvt tl o txd(6) transmit data cp n _6 table 6 1 lvt tl o txd(1) transmit data cp n+1 _0 table 6 1 nc nc nc nc cp n+1 _1 table 6 1 nc nc nc nc cp n+1 _2 table 6 1 lvt tl o txd(5) transmit data cp n+1 _3 table 6 1 lvt tl o txd(4) transmit data cp n+1 _4 table 6 1 lvt tl o txd(3) transmit data cp n+1 _5 table 6 1 lvt tl o txd(2) transmit data cp n+1 _6 table 6 1 lvt tl o txd(0) transmit data (ten bits wide, first on wire) cp n+2 _0 table 6 1 nc nc nc nc cp n+2 _1 table 6 1 lvt tl i rclk receive clock (62.5 mhz) cp n+2 _2 table 6 1 lvt tl i rxd(9) receive data (ten bits wide, last on wire) cp n+2 _3 table 6 1 lvt tl i rxd(8) receive data cp n+2 _4 table 6 1 lvt tl i rxd(7) receive data cp n+2 _5 table 6 1 lvt tl i rxd(6) receive data cp n+2 _6 table 6 1 lvt tl i rxd(1) receive data cp n+3 _0 table 6 1 nc nc nc nc cp n+3 _1 table 6 1 lvt tl i rclkn receive clock inverted f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pin descriptions grouped by function 37 motorola general business information C5NPD0-DS/d rev 04 sonet oc-3 transceiver interface configuration table 12 describes the sonet optical carrier (oc) 3 transceiver interface signals. for each cp (0-15), you can implement a single oc-3 interface. sonet oc-12 transceiver interface configuration sonet optical carrier (oc) 12 is implemented by using one cluster of cps. at any time, a cp within a cluster spends half its time performing receive functions, and the other half performing transmit functions. table 13 shows a cp cluster configured for one oc-12 interface. cp n+3 _2 table 6 1 lvt tl i rxd(5) receive data cp n+3 _3 table 6 1 lvt tl i rxd(4) receive data cp n+3 _4 table 6 1 lvt tl i rxd(3) receive data cp n+3 _5 table 6 1 lvt tl i rxd(2) receive data cp n+3 _6 table 6 1 lvt tl i rxd(0) receive data (ten bits wide, first on wire) total pins 28 * n can be 0, 4, 8, or 12 ? reference table 6 for pin numbers for the actual cluster(s) you are configuring. table 11 gigabit ethernet and fibre channel tbi signals example (continued) signal name* pin # ? total type i/o label signal description table 12 oc-3 signals signal name* pin # ? total type i/o label signal description cp n _0 table 6 1 lvpecl i rclk_h receive clock noninverted side of pair (155.52mhz) cp n _1 table 6 1 lvpecl i rclk_l receive clock inverted side of pair (155.52mhz) cp n _2 table 6 1 lvpecl o txd_h transmit data noninverted side of pair cp n _3 table 6 1 lvpecl o txd_l transmit data inverted side of pair cp n _4 table 6 1 lvpecl i rxd_h receive data noninverted side of pair cp n _5 table 6 1 lvpecl i rxd_l receive data inverted side of pair cp n _6 table 6 1 lvpecl i signal_det a light level above a certain threshold is present at the optical receiver - single ended lvpecl. total pins 7 * n can be from 0 to 15. ? reference table 6 for pin numbers for the actual cluster(s) you are configuring. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
38 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information table 13 oc-12 signals example signal name* pin # ? total type i/o label signal description cp n _0 table 6 1 lvt tl o tclk deskewed transmit clock (77.76mhz). this clock is used to synchronize the transmit data. cp n _1 table 6 1 lvt tl i tclk1 transceiver transmit clock. this clock sets the frequency of the transmit data and is typically sourced by the phy chip. cp n _2 table 6 1 lvt tl o txd(0) transmit data (byte-wide data, least significant bit) cp n _3 table 6 1 lvt tl o txd(1) transmit data cp n _4 table 6 1 lvt tl o txd(2) transmit data cp n _5 table 6 1 lvt tl o txd(3) transmit data cp n _6 table 6 1 lvt tl 0 00f out of frame cp n+1 _0 table 6 1 nc nc nc nc cp n+1 _1 table 6 1 nc nc nc nc cp n+1 _2 table 6 1 lvt tl o txd(4) transmit data cp n+1 _3 table 6 1 lvt tl o txd(5) transmit data cp n+1 _4 table 6 1 lvt tl o txd(6) transmit data cp n+1 _5 table 6 1 lvt tl o txd(7) transmit data (byte-wide data, most significant bit) cp n+1 _6 table 6 1 nc nc nc nc cp n+2 _0 table 6 1 nc nc nc nc cp n+2 _1 table 6 1 lvt tl i rclk receive clock (77.76mhz) cp n+2 _2 table 6 1 lvt tl i rxd(0) receive data (byte-wide receive data, least significant bit) cp n+2 _3 table 6 1 lvt tl i rxd(1) receive data cp n+2 _4 table 6 1 lvt tl i rxd(2) receive data cp n+2 _5 table 6 1 lvt tl i rxd(3) receive data cp n+2 _6 table 6 1 lvt tl i fp frame synchronization pulse. this is valid during the third a2 of the receive sonet frame. cp n+3 _0 table 6 1 nc nc nc nc cp n+3 _1 table 6 1 nc nc nc nc cp n+3 _2 table 6 1 lvt tl i rxd(4) receive data cp n+3 _3 table 6 1 lvt tl i rxd(5) receive data cp n+3 _4 table 6 1 lvt tl i rxd(6) receive data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pin descriptions grouped by function 39 motorola general business information C5NPD0-DS/d rev 04 executive processor system interface signals the xp ? s system interface manages the supervisory controls for the network interfaces, as well as the set of pins that provide interfaces to other components in the system that are not memories or network interfaces. it is also the primary interface used for initializing the c-5 np after reset. the xp signals include pci signals, serial interface signals, and prom interface signals. pci signals the pci can be configured to support a 32bit pci capable of operating at either 33mhz or 66mhz. the pci is fully compliant with pcvi specification revision 2.1. table 14 describes the pci signals. cp n+3 _5 table 6 1 lvt tl i rxd(7) receive data (most significant bit) cp n+3 _6 table 6 1 nc nc nc nc total pins 28 * n can be 0, 4, 8, or 12 ? reference table 6 for pin numbers for a different cluster. table 13 oc-12 signals example (continued) signal name* pin # ? total type i/o label signal description table 14 pci signals signal name pin # total type i/o signal description pad0 - pad31 t22, r21, p21, t21, r20, p20, t20, r19, q20, s20, r18, p19, t19, r17, p18, t18, r16, q18, s18, s16, p17, t17, r15, p16, t16, s14, q16, t15, r14, p15, t14, q14 32 pci i/o multiplexed address/data bus. these signals are multiplexed address and data bits. the c-5 np receives addresses as target and drives addresses as master. it drives the data and receives read data as master. pcbex0 - pcbex3 n21, n20, m20, o20 4 pci i/o command byte enables. these signals are multiplexed command and byte enabled signals. the c-5 np receives byte enables as target and drives byte enables as master. ppar p14 1 pci i/o parity. this signal carries even parity for ad and cbe# pins. it has the same receive and drive characteristics as the address and data bus, except that it is one pci cycle later. pframex k20 1 pci i/o cycle frame ptrdyx l20 1 pci i/o target ready for data transfer pirdyx l19 1 pci i/o initiator ready for data transfer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
40 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information serial interface signals the serial interface is a bidirectional two-wire serial bus. it can use one of the following formats: 1 an 8bit data format followed by an acknowledge bit, which supports transfers at up to 400kbps (low speed). 2 a 16bit ieee 802.3 mdio data format with 10bits of addressing, which supports transfers up to 25mhz (high speed). the signals and pins are identical for both the high and low speed protocols. which of the two data rates used is selected by the state of the prom interface ? s spld signal that is asserted while the prom interface is idle. when spld is asserted hi the low speed serial bus protocol is selected and when spld is asserted low the mdio protocol is selected. the bus only supports a single master hierarchy that can operate as either a receiver or a transmitter. the bus also supports collision detection and arbitration, and an integrated addressing and data-transfer protocol. both sida and sicl are bidirectional lines that are connected, through a pull-up resistor, to a positive supply voltage. when the bus is free, both lines are high. the output stages pstopx k18 1 pci i/o target transaction stop request pdevselx n18 1 pci i/o target device selected pperrx m18 1 pci i/o bus parity error pserrx l18 1 pci i/o system error pclk l15 1 pci i bus clock prstx n17 1 pci i bus reset preqx l17 1 pci o initiator bus request (arbitration) pgntx n19 1 pci i initiator bus grant (arbitration) pidsel o18 1 pci i initialization device select pinta o16 1 pci o interrupt total pins 50 table 14 pci signals (continued) signal name pin # total type i/o signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pin descriptions grouped by function 41 motorola general business information C5NPD0-DS/d rev 04 of the devices connected to the bus must have either an open-drain or open-collector in order to perform the wired-and function required for its arbitration mechanism. prom interface signals the prom interface is a low speed i/o port that allows the c-5 np to communicate through external logic to prom. the prom clock is 1 / 2 to 1 / 16 the core clock rate. the maximum prom size is 4mbytes x 16, and configuration is required. the prom signals are listed in table 16 . figure 4 shows the connections between the prom interface and external board logic. the application is required to provide an external shift register with parallel-in and parallel-out capabilities, and a parallel load register. both devices should be table 15 serial port signals signal name pin # total type i/o signal description sicl o14 1 lvt tl i/o serial clock line sida n14 1 lvt tl i/o serial data line total pins 2 table 16 prom interface signals signal name pin # total type i/o signal description spdo n15 1 lvt tl o serial data out spdi n16 1 lvt tl i serial data in spld m16 1 lvt tl o when load is asserted on a positive clock edge, the external logic performs a parallel load. on each positive clock edge when load is de-asserted, the shift registers shift. when the prom interface is idle: if spld is asserted hi it indicates low speed serial protocol, if asserted low it indicates mdio serial protocol. spck m14 1 lvt tl o clock total pins 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
42 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information positive-edge-triggered and perform a parallel load whenever spld is asserted. when spld is deasserted the shift register shifts. figure 4 prom interface diagram the prom interface operates in the following manner: two accesses are piplined together to execute one 32-bit fetch. the steps are shown in figure 5 . 1 the prom_addr is loaded into the network processor internal shift register. 2 the prom_addr is shifted into the external shift register for 22 spclk cycles. 3 spld is asserted for one spclk cycle, loading the prom_addr into the external presentation register. 4 spld is deasserted for 22 spclk cycles. the prom presents the first 16bit prom_data. at the same time, the next prom_addr is shifted into the external shift register. 5 spld is asserted for one spclk cycle, loading the prom_addr into the external presentation register and the first prom_data into the external shift register. 6 spld is deasserted for 22 spclk cycles, shifting the first prom_data into the network processor internal shift register. external logic prom_addr<21:1> 15 15 16 prom _h_word c-5 network processor prom clock gen. 31 21 21 6 1 0 prom _return_data prom sequencer 21 0 0 spclk spld spdo spdi internal shift register prom_addr<21:1> ce prom _lo_word 21 60 21 0 21 1 prom prom_data 16 external shift register ce f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pin descriptions grouped by function 43 motorola general business information C5NPD0-DS/d rev 04 7 spld is asserted for one spclk cycle, loading the first prom_data into the network processor prom_return_data register and the second prom_data into the external shift register. 8 spld is deasserted for 22 spclk cycles, shifting the second prom_data into the network processor internal shift register. 9 spld is asserted for one spclk cycle, loading the second prom_data into the network processor prom_return_data register. figure 5 prom interface timing outline general system interface signal table 17 provides the signal for the executive processor reset power status and i/o clock. the c-5 np can be powered up with the xp either running or with the xp in reset mode similar to the cps. when the xp remains in reset mode, an external host can be used to control the initialization of the c-5 np. spclk spld 12 456789 11 10 12 13 14 15 16 17 18 19 20 21 22 23 1234567891011 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 19 21 22 23 1 2 3 4 5 6 7 x a 20 a 19 a 18 spdto a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 ce the prom_addr is loaded into the c-5s internal shift register. the prom_addr is shifted into the external shift register. (spclk rising edge used for shifting) the prom_addr is loaded into the external presentation register. the prom_data is presenting. the prom_data is loaded into the external shift register. the prom_data is shifted into the c-5s internal shift register. the prom_data is loaded into the c-5s internal prom_return_data register. spdti x d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 xxxxxx xp prom interface outline xp prom interface detail spld spdto spdti a1 a2 a3 a4 a5 d1 d2 d3 d1 d2 a1 a2 a3 a4 1 2 3 4 5 6 7 8 9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
44 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information fabric processor interface signals the fp consists of two logical signal interfaces: a receive data interface and a transmit data interface, each with its own control and clocking signals. the interface has the following characteristics: the interface clocks frxclk and ftxclk can have a different frequency from the core c-5 np clock frequency. the fabric data processor (fdp) has synchronizing fifos at its interface boundary to allow for a fabric interface frequency from 10mhz to 110mhz. the receive clock frxclk and the transmit clock ftxclk must share the same frequency. the synchronization logic internal to the fp requires related clock domains on the transmit and receive interfaces. each of the two clocks can have different phase alignment, however, because they are generated externally. each data bus can be run at widths of 16 or 32 bits of data (fin0 - fin31 and fout0 - fout31) per clock. the extra data pins in each configuration remain unused. the output pins are driven to a known state, and the input pins should also be pulled to a known state. table 17 general system interface signal signal name pin # total type i/o signal description xpuhot j19 1 lvt tl i sample at power on reset determines if the xp risc core is held in reset. low equals reset and high equals active. during normal operation, this is an external interrupt. total pins 1 table 18 fabric interface signals signal name pin # total type i/o signal description fin0 - fin31 w2, v1, t1, v2, u2, v3, t3, t2, w4, v4, v5, u4, t4, w6, v6, u6, t5, t6, v7, t7, x8, w8, v8, v9, u8, x9, v10, u10, x10, w10, x11, v11 32 lvt tl i fabric data bus in fout0 - fout31 w28, v29, t29, v28, u28, v27, t27, t28, w26, v26, v25, u26, t26, w24, v24, u24, t25, t24, v23, t23, x22, w22, v22, v21, u22, x21, v20, u20, x20, w20, x19, v19 32 lvt tl o fabric data bus out frxclk w14 1 lvt tl i receive clock ftxclk w16 1 lvt tl i transmit clock frxctl0 - frxctl6 u12, w12, v12, x12, x13, v13, x14 7 lvt tl i, o receive control signals f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pin descriptions grouped by function 45 motorola general business information C5NPD0-DS/d rev 04 the following tables list the fabric interface pin mappings: utopia1, utopia2, utopia3 atm mode mappings are listed in table 19 utopia1, utopia2, utopia3 phy mode mappings are listed in table 20 prizma mode mappings are listed in table 21 (prizma mode is an example of utopia3 phy mode) power x mode mappings are listed in table 22 ftxctl0 - ftxctl6 u18, w18, v18, x18, x17, v17, x16 7 lvt tl i, o transmit control signals total pins 80 table 18 fabric interface signals (continued) signal name pin # total type i/o signal description table 19 utopia1*, 2*, 3 atm mode, c-5 network processor to fabric interface pin mapping receive signals transmit signals c-5 network processor i/o utopia note c-5 network processor i/o utopia note frxctl0 output rxenb* pullup or nc ftxctl0 output txenb* pullup or nc frxctl1 input rxclav pulldown ftxctl1 input txclav pulldown frxctl2 input rxsoc pulldown ftxctl2 output txsoc pulldown frxctl3 input n/a pullup or pulldown ftxctl3 nc nc frxctl4 input n/a ftxctl4 nc nc frxctl5 input n/a ftxctl5 nc nc frxctl6 input rxprty ftxctl6 output txprty * cell size must be 4byte aligned. table 20 utopia1*, 2*, 3 phy mode, c-5 network processor to fabric interface pin mapping receive signals transmit signals c-5 network processor i/o utopia note c-5 network processor i/o utopia note frxctl0 input txenb* pullup ftxctl0 input rxenb* pullup f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
46 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information when configuring two c-5 network processors back-to-back using the fabric port, set up the transmit side of each c-5 network processor in utopia atm mode and the receive side of each c-5 network processor in utopia phy mode. frxctl1 output txclav pulldown or nc ftxctl1 output rxclav pulldown or nc frxctl2 input txsoc pulldown ftxctl2 output rxsoc pulldown frxctl3 input n/a pullup or pulldown ftxctl3 nc nc frxctl4 input n/a pullup or pulldown ftxctl4 nc nc frxctl5 input n/a pullup or pulldown ftxctl5 nc nc frxctl6 input txprty ftxctl6 output rxprty * cell size must be 4byte aligned. table 20 utopia1*, 2*, 3 phy mode, c-5 network processor to fabric interface pin mapping receive signals transmit signals c-5 network processor i/o utopia note c-5 network processor i/o utopia note table 21 prizma mode, c-5 network processor to fabric interface pin mapping receive signals transmit signals c-5 network processor i/o utopia note c-5 network processor i/o utopia note frxctl0 input txenb* pulldown (not connected to fabric) ftxctl0 input rxenb* pulldown (not connected to fabric) frxctl1 output txclav nc ftxctl1 output rxclav nc frxctl2 input txsop pulldown ftxctl2 output rxsop pulldown frxctl3 input n/a pullup or pulldown ftxctl3 nc nc frxctl4 input n/a pullup or pulldown ftxctl4 nc nc frxctl5 input n/a pullup or pulldown ftxctl5 nc nc frxctl6 input txprty or nc ftxctl6 output rxprty or nc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pin descriptions grouped by function 47 motorola general business information C5NPD0-DS/d rev 04 bmu sdram interface signals the bmu and sdram interface signals are described in table 23 . the bmu is designed to support sdram devices with 12 address lines. all 139 data lines and all 12 address lines must be connected to the sdram in order for the bmu to be able to read and write external sdram properly. table 22 power x mode, c-5 network processor to fabric interface pin mapping receive signals transmit signals c-5 network processor i/o power x note c-5 network processor i/o power x note frxctl0 input rxctrl[0] pulldown ftxctl0 output txctrl[0] pulldown or nc frxctl1 input rxctrl[1] pulldown ftxctl1 output txctrl[1] pulldown or nc frxctl2 input rxctrl[2] pulldown ftxctl2 output txctrl[2] pulldown or nc frxctl3 input rxprty[3] ftxctl3 output txprty[3] frxctl4 input rxprty[2] ftxctl4 output txprty[2] frxctl5 input rxprty[1] ftxctl5 output txprty[1] frxctl6 input rxprty[0] ftxctl6 output txprty[0] table 23 bmu sdram interface signals signal name pin # total type i/o signal description md0 - md129 r29, q28, p28, s28, r28, p29, r27, q26, p26, s26, r26, p27, r25, q24, p24, s24, r24, p25, s22, r23, r22, n29, m28, l28, j29, o28, n28, l29, k28, n27, m26, l26, j28, o26, n26, l27, k26, n25, m24, l24, j27, o24, n24, l25, k24, p22, m22, k22, j23, q22, n23, l22, j25, o22, l23, j26, j22, p23, n22, l21, j24, b29, d29, f29, a28, c28, e28, g28, b28, d28, f28, b27, d27, f27, a26, c26, e26, b26, d26, f26, g26, b25, d25, f25, a24, c24, e24, b24, d24, f24, b23, d23, f23, g24, a22, c22, e22, b22, d22, f22, b21, d21, f21, a20, c20, e20, g22, b20, d20, f20, b19, d19, f19, a18, c18, e18, b18, d18, f18, g20, b17, d17, f17, a16, c16, e16, b16, d16, f16, b15 130 lvt tl i/o data lines in mdecc0 - mdecc8 g16, f15, f14, e14, d15, d14, c14, b14, a14 9 lvt tl i/o stored as data, ecc bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
48 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information ma0 - ma11 h22, i22, h23, h24, i24, h25, h26, i26, h27, h28, i28, h29 12 lvt tl o address outputs: a0-a11 are sampled during the active command and read/write to select one location out of the memory array in the respective bank. the address inputs also provide the op-code during a load mode register command mba0 - mba1 g18, h19 2 lvt tl o bank address outputs: ba0 and ba1 define which bank the active, read, write or precharge command is being applied mclk i16 1 nc nc reserved mcasx j21 1 lvt tl o command outputs: mrasx, mcasx, mwex and mcsx define the command being entered. note: mcsx is considered part of the command code. mrasx i20 1 lvt tl o command outputs: mrasx, mcasx, mwex and mcsx define the command being entered. mcsx is considered part of the command code. mwex j20 1 lvt tl o command outputs: mrasx, mcasx, mwex and mcsx define the command being entered. mcsx is considered part of the command code. mcsx h20 1 lvt tl o chip select: mcsx enables (registered low) and disables (registered high) the command decoder. all commands are masked when mcsx is registered high. mcsx provides the external bank selection on systems with multiple banks. mcsx is considered part of the command code. mdqm mdqml h21 g14 1 1 lvt tl lvt tl o o input/output mask: mdqm is an input mask signal for write accesses and an output enable signal for read accesses. input data is masked when mdqm is sampled high during a write cycle. the output buffers are placed in a high z state (two-clock latency) when mdqm is sampled high during the read cycle. note: mdqml is an identical copy of mdqm used to drive the loading on sdram configurations with 2 dqm pins. table 23 bmu sdram interface signals (continued) signal name pin # total type i/o signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pin descriptions grouped by function 49 motorola general business information C5NPD0-DS/d rev 04 tlu sram interface signals the tlu sram interface supports up to 32mbytes of sram at frequencies to 133mhz using lvttl signaling levels (in single bank-mode only) and sram technologies up to 64mbits. the tlu sram interface signals are described in table 24 . mdclk j17 1 lvt tl i clock: mdclk is driven by the system clock. all sdram input signals are sampled on the positive edge of the mdclk. mdclk also increments the internal burst counter and controls the output registers. total pins 161 table 23 bmu sdram interface signals (continued) signal name pin # total type i/o signal description table 24 tlu sram interface signals signal name pin # total type i/o signal description td0 - td63 n1, l1, j1, h1, m2, k2, i2, g2, n2, l2, j2, h2, l3, j3, h3, g4, 04, m4, k4, i4, l4, j4, h4, g6, n5, l5, j5, h5, n6, l6, i6, h6, k6, j6, m6, h7, l7, j7, h8, n8, m8, k8, i8, g8, n7, l8, j8, h9, l9, j9, j10, g10, p9, o8, l10, h10, o10, n9, l11, i10, m10, k10, j11, h11 64 lvt tl i/o tlu memory data ta0 - ta21 r1, p1, s2, q2, o2, r2, p2, r3, p3, n3, s4, q4, r4, p4, n4, r5, p5, s6, r6, q6, p6, o6 22 lvt tl o tlu memory address ta18x - ta21x t8, q8, r7, p7 4 lvt tl o data parity tce0x - tce3x p8, r8, s8, t9 4 lvt tl o tlu memory chip enable twe0x - twe3x q10, r9, s10, t10 4 lvt tl o tlu memory write enable tclki m12 1 lvt tl i tlu clock input total pins 99 table 25 memory bank selection chip select (signals ta18x through ta21x) size bank 1 bank 2 bank 3 bank 4 ce2 ce2x ce2 ce2x ce2 ce2x ce2 ce2x 4mbit ta18x ta19 ta18 ta19 ta18x ta19x ta18 ta19x 8mbit ta19x ta20 ta19 ta20 ta19x ta20x ta19 ta20x 16mbit ta20x ta21 ta20 ta21 ta20x ta21x ta20 ta21x f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
50 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information qmu sram interface signals the qmu signals are described in table 26 . the qmu ? s clock frequency is 1 / 2 the internal core clock frequency. power supply signals power supply and ground signals are described in table 27 and their pinouts are shown in figure 6 . table 26 qmu sram interface signals signal name pin # total type i/o* signal description qcpar a10 1 nc nc not used qclk g12 1 lvt tl o clock signal to the memory ics qcmd0 - qcmd15 b10, c10, d10, e10, f10, b11, d11, f11, a12, b12, c12, d12, e12, b13, d13, f13 16 lvt tl o memory address [15: 0] to the memory ics qdpar a8 1 lvt tl i/o data parity qdata0 - qdata31 d1, f1, f2, b2, c2, d2, e2, b3, d3, f3, a4, b4, c4, d4, e4, f4, b5, d5, f5, a6, b6, c6, d6, e6, f6, b7, d7, f7, c8, d8, e8, f8 32 lvt tl i/o memory data qsflow b9 1 lvt tl o not used qxctrl0 d9 1 lvt tl o rd/wr (read is true high, write is true low) qxctrl1 f9 1 lvt tl o memory address [16] to the memory ics qxrqst b8 1 nc nc reserved note: requires pullup or pulldown. total pins 55 * during normal (non-scan) operation. table 27 power supply signals signal name pin # total type signal description vdd a3, a11, a15, a23, a27, c1, c5, c13, c17, c25, c29, e3, e7, e15, e19, e27, g5, g9, g17, g21, g29, i7, i11, i19, i23, j12, k1, k9, k13, k21, k25, l14, m3, m11, m15, m23, m27, o1, o5, o13, o17, o25, o29, q3, q7, q15, q19, q27, s5, s9, s17, s21, s29, u7, u11, u19, u23, w1, w9, w13, w21, w25, y3, y11, y15, y23, y27, aa1, aa5, aa13, aa17, aa25, aa29, ac3, ac7, ac15, ac19, ac27 78 p core supply voltage (1.8v input) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pin descriptions grouped by function 51 motorola general business information C5NPD0-DS/d rev 04 vdd33 a7, a19, c9, c21, e11, e23, f12, g1, g13, g25, h14, i3, i15, i27, j16, k5, k17, k29, m7, m19, o9, o21, q11, q23, s1, s13, s25, u3, u15, u27, w5, w17, w29, y7, y19, aa9, aa21, ac11, ac23 39 p i/o supply voltage (3.3v input) vss a5, a9, a13, a17, a21, a25, a29, c3, c7, c11, c15, c19, c23, c27, e1, e5, e9, e13, e17, e21, e25, e29, g3, g7, g11, g19, g23, g27, h12, h16, i1, i5, i9, i13, i17, i21, i25, i29, j14, j18, k3, k7, k11, k15, k19, k23, k27, l16, m1, m5, m9, m13, m17, m21, m25, m29, o3, o7, o11, o15, o19, o23, o27, q1, q5, q9, q13, q17, q21, q25, q29, s3, s7, s11, s15, s19, s23, s27, u1, u5, u9, u13, u17, u21, u25, u29, w3, w7, w11, w15, w19, w23, w27, y1, y5, y9, y13, y17, y21, y25, y29, aa3, aa7, aa11, aa15, aa19, aa23, aa27, ac1, ac5, ac9, ac13, ac17, ac21, ac25, ac29 116 p ground total pins 234 table 27 power supply signals (continued) signal name pin # total type signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
52 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information figure 6 power and ground connections (bottom view) test signals test signals are described in table 28 and their pinouts are shown in figure 6 . vss (ground) - 0.0v vdd (core supply) - 2.5v vdd33 (i/o supply) - 3.3v ac ab aa z y x w v u t s r q p o n m l k j i h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2 5 26 27 28 29 other f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
signals grouped by pin number 53 motorola general business information C5NPD0-DS/d rev 04 during jtag, sclk and sclkx must remain as differential inputs. no connection pins no connection pins are listed in table 29 . signals grouped by pin number the c-5 np signals are listed by pin number in table 30 . table 28 miscellaneous test signals for jtag, scan, and internal test routines signal name pin # total type signal description jtck t11 1 lvt tl test clock jtms* z15 1 lvt tl test mode select. high selects modes as defined in the ieee 1149.1 jtag specification. jtrstx ? x15 1 lvt tl test reset (low active) jtdi ? ab15 1 lvt tl test data in jtdo v15 1 lvt tl test data out jhighz t12 1 lvt tl turns off all output drivers when high jclkbyp t13 1 lvt tl 1x or 2x clock mode select. low selects 1x, high selects 2x. jse s12 1 lvt tl scan enable. high enables scan test. js00-js09 l12, n13, n12, p13, p12, q12, r13, r12, r11, r10 10 lvt tl scan out pins total pins 18 * according to the ieee 1149.1 specification, the jtms, jtrst, and jtdi pins must have internal pullups. while the c-5 np does no t currently have pads with pullups, customers can pull up these three pins on the board. table 29 no connection pins signal name pin # total type signal description nc1 - nc11 i18, h17, h18, n10, p10, n11, p11, u14, v14, u16, v16 11 nc reserved for future functionality total pins 11 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
54 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information table 30 signals listed by pin number pin function pin function pin function pin function a 1-29 a1 not present a9 vss a17 vss a25 vss a2 not present a10 qcpar a18 md113 a26 md74 a3 vdd a11 vdd a19 vdd33 a27 vdd a4 qdata10 a12 qcmd8 a20 md103 a28 md64 a5 vss a13 vss a21 vss a29 vss a6 qdata19 a14 mecc8 a22 md94 a7 vdd33 a15 vdd a23 vdd a8 qdpar a16 md123 a24 md84 b 1-29 b1 not present b9 qsflow b17 md120 b25 md81 b2 qdata3 b10 qcmd0 b18 md116 b26 md77 b3 qdata7 b11 qcmd5 b19 md110 b27 md71 b4 qdata11 b12 qcmd9 b20 md107 b28 md68 b5 qdata16 b13 qcmd13 b21 md100 b29 md61 b6 qdata20 b14 mecc7 b22 md97 b7 qdata25 b15 md129 b23 md90 b8 qxrqst b16 md126 b24 md87 c 1-29 c1 vdd c9 vdd33 c17 vdd c25 vdd c2 qdata4 c10 qcmd1 c18 md114 cb26 md75 c3 vss c11 vss c19 vss c27 vss c4 qdata12 c12 qcmd10 c20 md104 c28 md65 c5 vdd c13 vdd c21 vdd33 c29 vdd c6 qdata21 c14 mecc6 c22 md95 c7 vss c15 vss c23 vss c8 qdata28 c16 md124 c24 md85 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
signals grouped by pin number 55 motorola general business information C5NPD0-DS/d rev 04 d 1-29 d1 qdata0 d9 qxctrl0 d17 md121 d25 md82 d2 qdata5 d10 qcmd2 d18 md117 d26 md78 d3 qdata8 d11 qcmd6 d19 md111 d27 md72 d4 qdata13 d12 qcmd11 d20 md108 d28 md69 d5 qdata17 d13 qcmd14 d21 md101 d29 md62 d6 qdata22 d14 mecc5 d22 md98 d7 qdata26 d15 mecc4 d23 md91 d8 qdata29 d16 md127 d24 md88 e 1-29 e1 vss e9 vss e17 vss e25 vss e2 qdata6 e10 qcmd3 e18 md115 e26 md76 e3 vdd e11 vdd33 e19 vdd e27 vdd e4 qdata14 e12 qcmd12 e20 md105 e28 md66 e5 vss e13 vss e21 vss e29 vss e6 qdata23 e14 mecc3 e22 md96 e7 vdd e15 vdd e23 vdd33 e8 qdata30 e16 md125 e24 md86 f 1-29 f1 qdata1 f9 qxctrl1 f17 md122 f25 md83 f2 qdata2 f10 qcmd4 f18 md118 f26 md79 f3 qdata9 f11 qcmd7 f19 md112 f27 md73 f4 qdata15 f12 vdd33 f20 md109 f28 md70 f5 qdata18 f13 qcmd15 f21 md102 f29 md63 f6 qdata24 f14 mecc2 f22 md99 f7 qdata27 f15 mecc1 f23 md92 f8 qdata31 f16 md128 f24 md89 table 30 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
56 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information g 1-29 g1 vdd33 g9 vdd g17 vdd g25 vdd33 g2 td7 g10 td51 g18 mba0 g26 md80 g3 vss g11 vss g19 vss g27 vss g4 td15 g12 qclk g20 md119 g28 md67 g5 vdd g13 vdd33 g21 vdd g29 vdd g6 td23 g14 mdqml g22 md106 g7 vss g15 sclkx g23 vss g8 td43 g16 mecc0 g24 md93 h 1-29 h1 td3 h9 td47 h17 nc2 h25 ma5 h2 td11 h10 td55 h18 nc3 h26 ma6 h3 td14 h11 td63 h19 mba1 h27 ma8 h4 td22 h12 vss h20 mcsx h28 ma9 h5 td27 h13 cclk5 h21 mdqm h29 ma11 h6 td31 h14 vdd33 h22 ma0 h7 td35 h15 sclk h23 ma2 h8 td38 h16 vss h24 ma3 i 1-29 i1 vss i9 vss i17 vss i25 vss i2 td6 i10 td59 i18 nc1 i26 ma7 i3 vdd33 i11 vdd i19 vdd i27 vdd33 i4 td19 i12 cclk3 i20 mrasx i28 ma10 i5 vss i13 vss i21 vss i29 vss i6 td30 i14 cclk4 i22 ma1 i7 vdd i15 vdd33 i23 vdd i8 td42 i16 mclk i24 ma4 table 30 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
signals grouped by pin number 57 motorola general business information C5NPD0-DS/d rev 04 j 1-29 j1 td2 j9 td49 j17 mdclk j25 md52 j2 td10 j10 td50 j18 vss j26 md55 j3 td13 j11 td62 j19 xpuhot j27 md40 j4 td21 j12 vdd j20 mwex j28 md32 j5 td26 j13 cclk1 j21 mcasx j29 md24 j6 td33 j14 vss j22 md56 j7 td37 j15 cclk2 j23 md48 j8 td46 j16 vdd33 j24 md60 k 1-29 k1 vdd k9 vdd k17 vdd33 k25 vdd k2 td5 k10 td61 k18 pstopx k26 md36 k3 vss k11 vss k19 vss k27 vss k4 td18 k12 cclk0 k20 pframex k28 md28 k5 vdd33 k13 vdd k21 vdd k29 vdd33 k6 td32 k14 cclk6 k22 md47 k7 vss k15 vss k23 vss k8 td41 k16 cclk7 k24 md44 l 1-29 l1 td1 l9 td48 l17 preqx l25 md43 l2 td9 l10 td54 l18 pserrx l26 md31 l3 td12 l11 td58 l19 pirdyx l27 md35 l4 td20 l12 jso0 l20 ptrdyx l28 md23 l5 td25 l13 cpref l21 md59 l29 md27 l6 td29 l14 vdd l22 md51 l7 td36 l15 pclk l23 md54 l8 td45 l16 vss l24 md39 table 30 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
58 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information m 1-29 m1 vss m9 vss m17 vss m25 vss m2 td4 m10 td60 m18 pperrx m26 md30 m3 vdd m11 vdd m19 vdd33 m27 vdd m4 td17 m12 tclki m20 pcbex2 m28 md22 m5 vss m13 vss m21 vss m29 vss m6 td34 m14 spck m22 md46 m7 vdd33 m15 vdd m23 vdd m8 td40 m16 spld m24 md38 n 1-29 n1 td0 n9 td57 n17 prstx n25 md37 n2 td8 n10 nc4 n18 pdevselx n26 md34 n3 ta9 n11 nc6 n19 pgntx n27 md29 n4 ta14 n12 jso2 n20 pcbex1 n28 md26 n5 td24 n13 jso1 n21 pcbex0 n29 md21 n6 td28 n14 sida n22 md58 n7 td44 n15 spdo n23 md50 n8 td39 n16 spdi n24 md42 o 1-29 o1 vdd o9 vdd33 o17 vdd o25 vdd o2 ta4 o10 td56 o18 pidsel o26 md33 o3 vss o11 vss o19 vss o27 vss o4 td16 o12 tclko o20 pcbex3 o28 md25 o5 vdd o13 vdd o21 vdd33 o29 vdd o6 ta21 o14 sicl o22 md53 o7 vss o15 vss o23 vss o8 td53 o16 pinta o24 md41 table 30 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
signals grouped by pin number 59 motorola general business information C5NPD0-DS/d rev 04 p 1-29 p1 ta1 p9 td52 p17 pad20 p25 md17 p2 ta6 p10 nc5 p18 pad14 p26 md8 p3 ta8 p11 nc7 p19 pad11 p27 md11 p4 ta13 p12 jso4 p20 pad5 p28 md2 p5 ta16 p13 jso3 p21 pad2 p29 md5 p6 ta20 p14 ppar p22 md45 p7 ta21x p15 pad29 p23 md57 p8 tce0x p16 pad23 p24 md14 q 1-29 q1 vss q9 vss q17 vss q25 vss q2 ta3 q10 twe0x q18 pad17 q26 md7 q3 vdd q11 vdd33 q19 vdd q27 vdd q4 ta11 q12 jso5 q20 pad8 q28 md1 q5 vss q13 vss q21 vss q29 vss q6 ta19 q14 pad31 q22 md49 q7 vdd q15 vdd q23 vdd33 q8 ta19x q16 pad26 q24 md13 r 1-29 r1 ta0 r9 twe1x r17 pad13 r25 md12 r2 ta5 r10 jso9 r18 pad10 r26 md10 r3 ta7 r11 jso8 r19 pad7 r27 md6 r4 ta12 r12 jso7 r20 pad4 r28 md4 r5 ta15 r13 jso6 r21 pad1 r29 md0 r6 ta18 r14 pad28 r22 md20 r7 ta20x r15 pad22 r23 md19 r8 tce1x r16 pad16 r24 md16 table 30 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
60 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information s 1-29 s1 vdd33 s9 vdd s17 vdd s25 vdd33 s2 ta2 s10 twe2x s18 pad18 s26 md9 s3 vss s11 vss s19 vss s27 vss s4 ta10 s12 jse s20 pad9 s28 md3 s5 vdd s13 vdd33 s21 vdd s29 vdd s6 ta17 s14 pad25 s22 md18 s7 vss s15 vss s23 vss s8 tce2x s16 pad19 s24 md15 t 1-29 t1 fin2 t9 tce3x t17 pad21 t25 fout16 t2 fin7 t10 twe3x t18 pad15 t26 fout12 t3 fin6 t11 jtck t19 pad12 tt27 fout6 t4 fin12 t12 jhighz t20 pad6 t28 fout7 t5 fin16 t13 jclkbyp t21 pad3 t29 fout2 t6 fin17 t14 pad30 t22 pad0 t7 fin19 t15 pad27 t23 fout19 t8 ta18x t16 pad24 t24 fout17 u 1-29 u1 vss u9 vss u17 vss u25 vss u2 fin4 u10 fin27 u18 ftxctl0 u26 fout11 u3 vdd33 u11 vdd u19 vdd u27 vdd33 u4 fin11 u12 frxctl0 u20 fout27 u28 fout4 u5 vss u13 vss u21 vss u29 vss u6 fin15 u14 nc8 u22 fout24 u7 vdd u15 vdd33 u23 vdd u8 fin24 u16 nc10 u24 fout15 table 30 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
signals grouped by pin number 61 motorola general business information C5NPD0-DS/d rev 04 v 1-29 v1 fin1 v9 fin23 v17 ftxctl5 v25 fout10 v2 fin3 v10 fin26 v18 ftxctl2 v26 fout9 v3 fin5 v11 fin31 v19 fout31 v27 fout5 v4 fin9 v12 frxctl2 v20 fout26 v28 fout3 v5 fin10 v13 frxctl5 v21 fout23 v29 fout1 v6 fin14 v14 nc9 v22 fout22 v7 fin18 v15 jtdo v23 fout18 v8 fin22 v16 nc11 v24 fout14 w 1-29 w1 vdd w9 vdd w17 vdd33 w25 vdd w2 fin0 w10 fin29 w18 ftxctl1 w26 fout8 w3 vss w11 vss w19 vss w27 vss w4 fin8 w12 frxctl1 w20 fout29 w28 fout0 w5 vdd33 w13 vdd w21 vdd w29 vdd33 w6 fin13 w14 frxclk w22 fout21 w7 vss w15 vss w23 vss w8 fin21 w16 ftxclk w24 fout13 x 1-29 x1 cp15_0 x9 fin25 x17 ftxctl4 x25 cp14_4 x2 cp15_1 x10 fin28 x18 ftxctl3 x26 cp14_3 x3 cp15_2 x11 fin30 x19 fout30 x27 cp14_2 x4 cp15_3 x12 frxctl3 x20 fout28 x28 cp14_1 x5 cp15_4 x13 frxctl4 x21 fout25 x29 cp14_0 x6 cp15_5 x14 frxctl6 x22 fout20 x7 cp15_6 x15 jtrstx x23 cp14_6 x8 fin20 x16 ftxctl6 x24 cp14_5 table 30 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
62 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information y 1-29 y1 vss y9 vss y17 vss y25 vss y2 cp13_0 y10 cp13_4 y18 cp12_5 y26 cp12_1 y3 vdd y11 vdd y19 vdd33 y27 vdd y4 cp13_1 y12 cp13_5 y20 cp12_4 y28 cp12_0 y5 vss y13 vss y21 vss y29 vss y6 cp13_2 y14 cp13_6 y22 cp12_3 y7 vdd33 y15 vdd y23 vdd y8 cp13_3 y16 cp12_6 y24 cp12_2 z 1-29 z1 cp9_0 z9 cp11_1 z17 cp10_5 z25 cp8_4 z2 cp9_1 z10 cp11_2 z18 cp10_4 z26 cp8_3 z3 cp9_2 z11 cp11_3 z19 cp10_3 z27 cp8_2 z4 cp9_3 z12 cp11_4 z20 cp10_2 z28 cp8_1 z5 cp9_4 z13 cp11_5 z21 cp10_1 z29 cp8_0 z6 cp9_5 z14 cp11_6 z22 cp10_0 z7 cp9_6 z15 jtms z23 cp8_6 z8 cp11_0 z16 cp10_6 z24 cp8_5 aa 1-29 aa1 vdd aa9 vdd33 aa17 vdd aa25 vdd aa2 cp7_0 aa10 cp7_4 aa18 cp6_5 aa26 cp6_1 aa3 vss aa11 vss aa19 vss aa27 vss aa4 cp7_1 aa12 cp7_5 aa20 cp6_4 aa28 cp6_0 aa5 vdd aa13 vdd aa21 vdd33 aa29 vdd aa6 cp7_2 aa14 cp7_6 aa22 cp6_3 aa7 vss aa15 vss aa23 vss aa8 cp7_3 aa16 cp6_6 aa24 cp6_2 table 30 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
jtag support 63 motorola general business information C5NPD0-DS/d rev 04 jtag support the c-5 np contains jtag test logic compliant with the ieee 1149.1 specification. all required public instructions are implemented, as well as some optional instructions. this section contains information regarding the pinout, instructions, identification codes, and boundary scan cell types. pinout the c-5 np uses the standard jtag pins including the optional test reset pin. table 28 describes the pins and their functions. note that pins for jtrstx, jtdi, and jtms require external pullups on the board. these ports do not have internal pullups as required by the 1149.1 specification. ab 1-29 ab1 cp3_0 ab9 cp5_1 ab17 cp4_5 ab25 cp2_4 ab2 cp3_1 ab10 cp5_2 ab18 cp4_4 ab26 cp2_3 ab3 cp3_2 ab11 cp5_3 ab19 cp4_3 ab27 cp2_2 ab4 cp3_3 ab12 cp5_4 ab20 cp4_2 ab28 cp2_1 ab5 cp3_4 ab13 cp5_5 ab21 cp4_1 ab29 cp2_0 ab6 cp3_5 ab14 cp5_6 ab22 cp4_0 ab7 cp3_6 ab15 jtdi ab23 cp2_6 ab8 cp5_0 ab16 cp4_6 ab24 cp2_5 ac 1-29 ac1 vss ac9 vss ac17 vss ac25 vss ac2 cp1_0 ac10 cp1_4 ac18 cp0_5 ac26 cp0_1 ac3 vdd ac11 vdd33 ac19 vdd ac27 vdd ac4 cp1_1 ac12 cp1_5 ac20 cp0_4 ac28 cp0_0 ac5 vss ac13 vss ac21 vss ac29 vss ac6 cp1_2 ac14 cp1_6 ac22 cp0_3 ac7 vdd ac15 vdd ac23 vdd33 ac8 cp1_3 ac16 cp0_6 ac24 cp0_2 table 30 signals listed by pin number (continued) pin function pin function pin function pin function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
64 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information jtag data registers the c-5 np contains the standard internal registers as specified in ieee 1149.1. these registers are described in table 31 . boundary scan cell types the c-5 np boundary scan register contains only two cell types. all input cells are observe only cells of type bc_4. all enable and output cells are standard cells of type bc_1. in ieee 1149.1-1990 specification, the bc_4 cell is shown in figure 7 and the bc_1 cell is shown in figure 8 . figure 7 observe-only cell table 31 jtag internal register descriptions register name register length description bypass 1 standard jtag bypass register boundary 1807 boundary scan register device identification 32 standard jtag idcode register g1 0 1 1d c1 from system pin to next cell to s y s t e m logic shift dr from last cell clock dr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
jtag support 65 motorola general business information C5NPD0-DS/d rev 04 figure 8 cell design that can be used for both input and output pins idcode register the c-5 np implements a standard 32bit jtag identification register. table 32 lists the value of the code for full identification and its sub-components. the concatenated 32bit value is hexidecimal 0000232d. jtag instruction register the c-5 np contains a 4bit instruction register. table 33 lists the instructions that are supported. g1 0 1 1d c1 from system pin to next cell to system logic shift dr from last cell clock dr 1d c1 g1 0 1 update dr node table 32 jtag identification code and its sub-components field name width bit positions binary value version 4 31-28 0000 part number 16 27-12 0000_0000_0000_0010 manufacturer identity 11 11-1 001_1001_0110 lsb 1 0 1 table 33 instruction register instructions instruction mnemonic selected register instruction opcode extest boundary scan 0000 idcode identification register 0001 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
66 chapter 2: signal descriptions C5NPD0-DS/d rev 04 motorola general business information boundary scan description language in order to simplify board test, c-port corporation has provided a boundary scan description language (bsdl) file in the c-port web site support area that describes the complete set of instructions, boundary scan order, and identification code value in an industry standard format. this information can be found at: http://e-www.motorola.com/webapp/sps/site/homepage.jsp?nodeid=03m0ylgx1ks. sample/preload boundary scan 0010 highz bypass register 0011 clamp bypass register 0100 bypass bypass register 0101 reserved* bypass register 0110 reserved* bypass register 0111 bypass bypass register 1000 bypass bypass register 1001 bypass bypass register 1010 bypass bypass register 1011 bypass bypass register 1100 bypass bypass register 1101 bypass bypass register 1110 bypass bypass register 1111 * there are two reserved instructions intended for c-port corporation ? s internal use. these should not be programmed by users. table 33 instruction register instructions (continued) (continued) instruction mnemonic selected register instruction opcode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola general business information C5NPD0-DS/d rev 04 C5NPD0-DS/d rev 04 chapter 3 electrical specifications absolute maximum ratings table 34 lists the absolute maximum ratings for the c-5 network processor. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and do not imply that operation under any conditions other than those listed under ? recommended operating conditions ? ( table 35 ) is possible. exposure to conditions beyond table 34 can: reduce device reliability result in premature device failure, even with no immediate sign of failure prolonged exposure to conditions at or near the absolute maximum ratings could also result in reduced useful life and reliability of the c-5 np. table 34 c-5 network processor absolute maximum ratings parameter min max unit v dd33 supply voltage (3.3v input)* ? * voltages are relative to ground ? not to exceed v dd + 2.5v -0.5 +5 v v dd supply voltage (1.8v input)* -0.5 +2.8 v voltage on any pin -0.5 v dd33 + 0.5 v static discharge voltage 2000/500 v storage temperature -40 +125 c absolute maximum junction temperature -40 +125 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
68 chapter 3: electrical specifications C5NPD0-DS/d rev 04 motorola general business information recommended operating conditions the recommended operating conditions describe an environment the c-5 np network processor is expected to encounter during normal operation. table 35 delineates the recommended operating parameters for the c-5 np. dc characteristics the dc electrical characteristics define the input operating conditions for proper operation and the output responses to applied dc signals and switch characteristics over specified voltage and temperature ranges. the dc electrical characteristics are specified within the recommended operating conditions including operating temperature and power supply range as stated in this data sheet. table 36 outlines the c-5 np dc characteristics. table 35 c-5 network processor recommended operating conditions parameter min max unit v dd33 supply voltage 3.135 3.465 v v dd supply voltage 1.7 1.9 v i dd33 - v dd33 supply current 1.5* * peak values to be used by power supply designer. a i dd - v dd supply current 14* a t j junction temperature -40 100 c table 36 c-5 network processor dc characteristics parameter* min max unit notes lvt tl input high voltage 2.0 v dd33 +.3 v lvttl input low voltage -0.3 0.8 v lvt tl output high voltage 2.4 v @i oh = -2ma lvttl output low voltage 0.4 v @i ol = +2ma lvttl input current -5 +5 a v in = 0v or v dd33 lvpecl input high voltage v dd33 -1.165 v dd33 +.3v v lvpecl input low voltage -0.3 v dd33 -1.475 v lvpecl output high voltage v dd33 -1.025 v dd33 -0.880 v load = 50ohm to v dd33 - 2v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
power sequencing 69 motorola general business information C5NPD0-DS/d rev 04 each control input pin has a capacitance associated with it. the capacitance at the control input is due to the package and the input circuitry connected to the pin. capacitance is based on these conditions: t a = 25 c ; v dd33 = 3.3v; f = 1mhz. table 37 provides capacitance data. power sequencing the vdd rail must be kept within 2.5v of the vdd33 rail. however, this rule can be violated for periods up to one second, as is typical during power sequencing, as long as: the vdd is not clamped to ground or some other low voltage. the number of power cycling events averages to less than once per day over the lifetime of the product. it is intended that the vdd and vdd33 rail be sequenced to their final value together for most applications. it is also required that sclk, sclkx, tclki, pclk, mdclk, ftxclk, and frxclk be running or begin running during power sequencing to propagate reset inside the c-5 np. figure 9 indicates the relationship between the clocks and prstx. there is no requirement that the asserting and deasserting edges of prstx be synchronous to the clocks. reset must be asserted within 100 s of power initiation. typically, reset is held low during power initiation. lvpecl output low voltage v dd33 -1.810 v dd33 -1.620 v load = 50ohm to v dd33 - 2v lvpecl input current -5 +5 a cpref v dd33 -1.38 v dd33 -1.26 v single-ended lvpecl reference * all voltages are relative to ground unless otherwise indicated. table 37 c-5 network processor capacitance data parameter typical max unit input/output pins 7 8 pf input pins 6 7 pf clock pins 6 7 pf table 36 c-5 network processor dc characteristics (continued) (continued) parameter* min max unit notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
70 chapter 3: electrical specifications C5NPD0-DS/d rev 04 motorola general business information figure 9 bringup clock timing diagram power and thermal characteristics table 38 provides the derived power and thermal characteristics for the production version (revision d0) of the c-5 np. tclki, pclk, sclk, sclkx, dclk, ftxclk, frxclk prstx ? 1ms ? 100ms ( ( ) ) 100ms vdd, vdd33 table 38 c-5 network processor power and thermal characteristics parameter min typ max units test conditions power dissipation, p d 10.5 11.5 12.5 14.5 15.0 16.0 17.5 20.0 18.0 19.0 20.5 23.0 w 166mhz core clock (see note 1) 180mhz core clock (see note 1) 200mhz core clock (see note 1) 233mhz core clock (see note 1) maximum junction temperature, t j 100 o c thermal resistance, junction to case, jc 0.24 o c/w see note 2 thermal resistance, junction to ambient, ja 1.87 o c/w see note 2 thermal resistance, junction to printed circuit board, jb 4.8 o c/w see note 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
power and thermal characteristics 71 motorola general business information C5NPD0-DS/d rev 04 notes for table 38 : 1 estimated power dissipation (+/-10%) is derived from measurements on the c-5 np revision d00 under following conditions: bmu memory operating at 125mhz. tlu memory operating at 133mhz. v dd = 1.8v, v dd33 = 3.3v, t j at approximately 50 o c. ? minimum ? p d based on idle condition (clocks running and no programs executing). ? typical ? p d based on test application that implements fast ethernet forwarding actively running on all cps. ? maximum ? p d based on projected maximum consumption for any high-bandwidth communications application executing on all cps, fp, and xp. 2 thermal performance specifications based on following conditions: printed circuit board is based on the c-ware development system ? s c-5 np switch module reference design, with specifications of: ? 14 total layers (5 planes). planes at least 100mm x 100mm below the c-5 np before any interruptions. ? fr4 board material, cu signal and plane material. ? 0.5mils signal layer thickness, 1.4mils plane layer thickness. ? thermal resistance, board to ambient ( ba ) of 1.2 o c/w. custom heat sink design has the following characteristics: thermal resistance, junction through board to ambient, jba 6.0 see note 2 effective thermal resistance, effective 1.43 o c/w see note 3 table 38 c-5 network processor power and thermal characteristics (continued) parameter min typ max units test conditions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
72 chapter 3: electrical specifications C5NPD0-DS/d rev 04 motorola general business information ? dimensions: 100mm x 80mm x 10mm (height) ? thermal resistance heat sink to ambient ( sa ) of 1.6 o c/w @200 lfm. figure 10 provides the characteristic thermal resistance curve for this heat sink for various airflow rates. ? thermal resistance case to heat sink ( cs ) of 0.03 o c/w (chromerics t705 thermal material). ? note that target heat sink design is for low profile (10mm height) applications. significantly better thermal performance is possible with taller and/or wider designs. contact your c-port representative for heat sink options. 3 effective thermal resistance ( effective = ja jba / ( ja + jba )) reflects the total thermal performance of the heat sink and board, as outlined in note 2 above. figure 10 thermal performance for c-5 network processor heat sink (see step 2 above) ac timing specifications ac timing specifications consist of input requirements and output responses. the input requirements include setup and hold times, pulse widths, and high and low times. the output responses include delays from clock to signal. the ac timing specifications are defined separately for each interface to the c-5 np unless otherwise noted, all ac specifications were tested within the functional operating range. 0 200 400 600 800 1000 0 1 2 3 velocity (ft/min) thermal resistance ( c/w) theoretical calculation of thermal resistance as a function of airflow velocity across heat sink f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
ac timing specifications 73 motorola general business information C5NPD0-DS/d rev 04 see figure 11 . output timing specifications for lvttl pins are given with a 10pf load on the output. other loads can be simulated with the ibis model available from c-port. the lvpecl driver is specified into a 50 ? load terminated to a (vdd33 - 2v) reference. figure 11 test loading conditions clock timing specifications the system clock timing is shown in figure 12 and described in table 39 . figure 12 system clock timing diagram + 2v lvttl lvpecl dut dut 10pf 50 ? vdd33 t sc t sh sclk cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 sclkx cclkn t ccn t sl t cch t ccl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
74 chapter 3: electrical specifications C5NPD0-DS/d rev 04 motorola general business information unused clocks should be pulled to a known state (ground) through a resistor. if you are using a clock generator, disabling the output should not cause a tristate. if it does, then the line should be pulled down. cp timing specifications this section describes the timing for the following cp interfaces: ds1/ds3 ethernet timing description 10/100 ethernet timing description gigabit gmii/mii ethernet interface timing description oc-3 timing description table 39 system clock timing description symbol parameter min typ max unit comment 1x clk mode 2x clk mode 1x clk mode 2x clk mode tsc system cycle time 6.0 5.0 4.3 3.0 2.5 2.14 ns 166mhz core clock 200mhz core clock 233mhz core clock tsh sys clk high pulse 45 30 55 70 duty cycle* tsl sys clk low pulse 45 30 55 70 duty cycle ? tcc0 cclk0 cycle time 647.67 ns t1 ? tcc1 cclk1 cycle time 488.28 ns e1 ? tcc2 cclk2 cycle time 29.097 ns e3 ? tcc3 cclk3 cycle time 22.353 ns t3 ? tcc4 cclk4 cycle time 20.00 ns rmii ? tcc5 cclk5 cycle time 9.412 ns fibre channel ? tcc6 cclk6 cycle time 8.00 ns gmii ? tcc7 cclk7 cycle time 6.43 ns oc-3 ? tcch cclkm high time 40% 40% 60% 60% % cycle pulse is high tccl cclkm low time 40% 40% 60% 60% % cycle pulse is low * pulse duty cycle measured at crossing voltage of sclk/sclkx ? the frequencies specified for cclk0 - cclk7 allow full flexibility for the c-5 np . clock inputs associated with a specific pro tocol should be tied to ground when that protocol is not used by the c-5 np . it is also possible to use one or more cclk n inputs for other frequencies; contact your c-port representative for more information. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
ac timing specifications 75 motorola general business information C5NPD0-DS/d rev 04 gigabit tbi interface timing description oc-12 timing description ds1/ds3 timing specifications the ds1/ds3 interface timing is shown in figure 13 and described in table 40 . figure 13 ds1/ds3 ethernet timing diagram 10/100 ethernet timing specifications the 10/100 ethernet interface timing is shown in figure 14 and described in table 41 . cpn_0 (tclk) cycle 1 cycle 2 cycle 2 cycle 3 cycle 3 cycle 4 cycle 4 cycle 5 cycle 5 cpn_2/3 (tx) cpn_1 (rclk) cpn_4/5 (rx) t cdt t cdo t cdr t cds t cdh table 40 ds1/ds3 ethernet timing description symbol parameter min typ max unit tcdt ds1/ds3 transmit cycle time 647/22.4 ns tcdo ds1/ds3 output time 3.0/3.0 400/15.0 ns tcdr ds1/ds3 receive cycle time 647/22.4 ns tcds ds1/ds3 setup time 2.0 ns tcdh ds1/ds3 hold time 2.5 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
76 chapter 3: electrical specifications C5NPD0-DS/d rev 04 motorola general business information figure 14 10/100 ethernet timing diagram gigabit gmii ethernet, tbi and mii interface timing specifications the gigabit gmii ethernet interface timing is shown in figure 15 and described in table 42 . the tbi interface timing is shown in figure 15 and described in table 43 . cpn_0 (tclk) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cpn_2/3/6 (tx) cpn_1/4/5 (rx) t cet t ceo t ces t ceh table 41 10/100 ethernet timing description symbol parameter min typ max unit tcet transmit cycle time* * std/fast ethernet 20 ns tceo output time 3.0 15.0 ns tces setup time 2.0 ns tceh hold time 2.5 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
ac timing specifications 77 motorola general business information C5NPD0-DS/d rev 04 figure 15 gigabit ethernet and tbi interface timing diagram mii cpn_1 (tclk) cycle 1 cycle 2 cycle 3 mii cpn_2-6 (tx) t cmt t cmo mii tx cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cpn+2_1 (rclk) t cgr t cgs t cgh gmii rx cpn+2_2-6 (rx) cpn+3_2-6 (rx) cpn_0 (tclk) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 t cgt t cgo gmii / tbi tx cpn_2-6 (tx) cpn+1_2-6 (tx) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 t ctr t ctd t cts t cth tbi rx cpn+2_1 (rclkn) cpn+3_1 (rclk) cpn_2-6 (rx) cpn+1_2-6 (rx) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
78 chapter 3: electrical specifications C5NPD0-DS/d rev 04 motorola general business information oc-3 timing specifications the oc-3 interface timing is shown in figure 16 and described in table 44 . table 42 gigabit gmii/mii ethernet interface timing description symbol gigabit parameter min typ max unit comment tcgt transmit cycle time, gmii 8.0 ns tcgo output time, gmii 3.0 6.0 ns tcgr receive cycle time 8.0 ns tcgs setup time 1.5 ns tcgh hold time 0.5 ns tcmt transmit cycle time, mii 40/400 ns 100baset/10baset tcmo output time, mii 2 12 ms table 43 gigabit tbi interface timing description symbol tbi parameter min typ max unit tctt transmit cycle time 8.0 ns tcto output time 3.0 6.0* * for fibre channel applications this value is 7.0ns for a transmit cycle time of 9.4ns. ns tctr receive cycle time 16.0 ns tctd rclk/rclkn deviation 1.0 ns tcts setup time 1.5 ns tcth hold time 0.5 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
ac timing specifications 79 motorola general business information C5NPD0-DS/d rev 04 figure 16 oc-3 timing diagram cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cpn_2 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cpn_3 cpn_0 cpn_1 cpn_4 cpn_5 t c3t t c3r t c3d t c3i t c3s t c3h t c3s t c3h table 44 oc-3 timing description symbol parameter min typ max unit tc3t oc-3 transmit cycle time 6.43 ns tc3i oc-3 pulse width 2.0 ns tc3r oc-3 receive cycle time* * 155.52mhz 6.0 ns tc3d oc-3 clock duty cycle 40 60 % tc3s oc-3 setup time 2.0 ns tc3h oc-3 hold time 2.5 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
80 chapter 3: electrical specifications C5NPD0-DS/d rev 04 motorola general business information oc-12 timing specifications the oc-12 interface timing is shown in figure 17 and described in table 45 . figure 17 oc-12 timing diagram cpn_1 (tclki) cycle 1 cycle 1 cycle 2 cycle 3 cycle 3 cycle 4 cycle 5 cpn_0 (tclk) cpn_2-6 (tx) cpn_1 (rclk) cpn_2-6 (rx) t c12i t c12t t c12r t c12o t c12s t c12h cycle 2 t c12d table 45 oc-12 timing description symbol parameter min typ max unit tc12i oc-12 transmit cycle time* * input from phy 12.86 ns tc12d oc-3 clock duty cycle 40 60 % tc12t oc-12 transmit cycle time ? ? output from c-5 np 12.86 ns tc12o oc-12 output time ? ? aligned to tclk 3.0 10.0 ns tc12r oc-12 receive cycle time 12.0 12.86 ns tc12s oc-12 setup time 2.0 ns tc12h oc-12 hold time 2.5 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
ac timing specifications 81 motorola general business information C5NPD0-DS/d rev 04 executive processor timing specifications the xp timing specifications include: pci timing specifications mdio serial interface timing specifications low speed serial interface timing specifications prom interface timing specifications pci timing specifications the pci timing is shown in figure 18 and described in table 46 . figure 18 pci timing diagram pclk cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 pad/p_ctl (output) pad/p_ctl (input) pgntx (input) pidsel (input) t pc t pao t pav t paz t pas t pah t pgs t pgh t pis t pih table 46 pci timing description symbol parameter min typ max unit tpc pci cycle time* 15.0 ns tpas pad/p_c tl ? setup 3.0 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
82 chapter 3: electrical specifications C5NPD0-DS/d rev 04 motorola general business information mdio serial interface timing specifications the mdio serial interface timing is shown in figure 19 and described in table 47 . figure 19 mdio serial interface timing diagram tpah pad/p_ctl hold 0.0 ns tpao pad/p_c tl output 2.0 6.0 ns tpaz pad/p_c tl clk to tri ? 1.8 5.5 ns tpav pad/p_ctl clk to driven ? 1.3 5.5 ns tpgs pgntx setup 5.1 ns tpgh pgntx hold 0.0 ns tpis pidsel setup 5.0 ns tpih pidsel hold 0.0 ns prstx** ns pinta** ns * 66mhz pci ? p_ctl includes all pci control parameters including: ppar, pframex, ptrdyx, pirdyx, pstopx, pdevselx, pperrx, pserrx ? not fully tested, values based on design/characterization. ** asynchronous table 46 pci timing description (continued) (continued) symbol parameter min typ max unit cycle 2 cycle 3 cycle 4 t sic t sids sicl sida (output) sida (input) t sods t sodh f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
ac timing specifications 83 motorola general business information C5NPD0-DS/d rev 04 low speed serial interface timing specifications the low speed serial interface timing is shown in figure 20 and described in table 48 . figure 20 low speed serial interface timing diagram table 47 mdio serial interface timing description symbol parameter min typ max unit tsic sicl cycle time 40 ns tsids sida input setup 10 ns tsidh sida input hold 0.0 ns tsods sida output setup 10 ns tsodh sida output hold 10 ns cycle 2 cycle 3 t cyc t su:s t hd:d t su:d t hd:s sicl sida t su:stop t buf table 48 low speed serial interface timing description symbol parameter min max unit tcycle sicl cycle time 2500 ns tsu:s set-up time for repeated start condition 600 ns thd:s hold time start condition 600 ns tsu:d data set-up time 250 ns thd:d data hold time 0.0 ns tsu:stop set-up time for stop condition 600 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
84 chapter 3: electrical specifications C5NPD0-DS/d rev 04 motorola general business information prom interface timing specifications the prom interface timing is shown in figure 21 and described in table 49 . figure 21 prom interface timing diagram tbuf bus free time between a stop and start condition 1250 ns cmax capacitive load for each line of the bus 400 pf table 48 low speed serial interface timing description (continued) (continued) symbol parameter min max unit spck cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 spdi spld spdo t spc t splo t spis t spih t spdo table 49 prom interface timing description symbol parameter clock mode min typ max unit tspc spck cycle time 40.0 ns tspis spdi setup 10.0 ns tspih spdi hold 0.0 ns tsplo spld output 1x tsc* * tsc is the system cycle time. see table 39 on page 74 tsc + 3.0 ns 2x 2 x tsc* 2 x tsc + 3.0 ns tspdo spdo output 1x tsc* tsc + 3.0 ns 2x 2 x tsc* 2 x tsc + 3.0 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
ac timing specifications 85 motorola general business information C5NPD0-DS/d rev 04 fabric processor timing specifications the fp timing specifications are shown in figure 22 and described in table 50 . figure 22 fabric processor timing diagram frxclk cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 frxctl (output) frxctl (input) finn t frc t frco t frcv t frcz t frcs t frch t frds t frdh t ftcs t ftch ftxclk ftxctl (output) ftxctl (input) foutn t ftc t ftco t ftcv t ftcz t ftdo table 50 fabric processor timing description symbol parameter min typ max unit comment tfrc frx cycle time 9.0 ns tfrcs frxctl setup 4.0 1.5 ns utopia2 mode all other modes tfrch frxctl hold 0.5 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
86 chapter 3: electrical specifications C5NPD0-DS/d rev 04 motorola general business information bmu timing specifications the bmu timing specifications are shown in figure 23 and described in table 51 . the bmu synchronous dram interface is pc100-compliant and designed to work with industry standard sdram components with 12 or fewer address lines. the information below is intended to provide the output, setup, and hold data required to design this interface without duplicating the transaction waveform diagrams in sdram data sheets. tfrco frxctl output 1.0 3.4 ns tfrcz frxctl clk to tri* 1.8 5.5 ns tfrcv frxctl clk to driven* 1.3 5.5 ns tfrds fin setup 4.0 1.5 ns utopia2 mode all other modes tfrdh fin hold 0.5 ns tftc ftx cycle time 9.0 ns tftcs ftxctl setup 4.0 1.5 ns utopia2 mode all other modes tftch ftxctl hold 0.5 ns tftco ftxctl output 1.0 3.6 ns tftcz ftxctl clk to tri* 1.7 5.5 ns tftcv ftxctl tri to driven* 1.3 5.5 ns tftdo fout output 1.0 3.6 ns * not fully tested, values based on design/characterization. table 50 fabric processor timing description (continued) symbol parameter min typ max unit comment f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
ac timing specifications 87 motorola general business information C5NPD0-DS/d rev 04 figure 23 bmu timing diagram mdclk cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 m_ctl man mdn (output) mdn (input) t mc t mdo t mco t mao t mdv t mds t mdz t mdh table 51 bmu timing description symbol parameter min typ max unit tmc bmu cycle time 8.0 ns tmco bmu ctrl output 1.2 3.7 ns tmao bmu addr output 1.2 3.8 ns tmds bmu data setup 0.5 ns tmdh bmu data hold 1.0 ns tmdo bmu data output 1.2 4.0 ns tmdz bmu data clk to tri* * not fully tested, values based on design/characterization. 1.8 4.0 ns tmdv bmu data clk to driven* 1.4 4.0 ns table 52 signal groups in bmu timing diagrams signal group included signals control (m_ctl) mba0, mba1, mcasx, mrasx, mwex, mcsx, mdqm address (man) ma0 - ma11 data (mdn) md0 - md129, mdecc0 - mdecc8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
88 chapter 3: electrical specifications C5NPD0-DS/d rev 04 motorola general business information tlu timing specifications the tlu timing specifications are shown in figure 24 and described in table 53 . figure 24 tlu timing diagram tclki cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 t_ctl tan tdn (output) tdn (input) t tc t tdo t tco t tao t tdv t tds t tdz t tdh table 53 tlu timing description symbol parameter min typ max unit ttc tlu cycle time 7.5 ns ttco tlu ctrl output 1.2 3.4 ns ttao tlu addr output 1.2 3.4 ns ttds tlu data setup 0.5 ns ttdh tlu data hold 1.0 ns ttdo tlu data output 1.2 3.5 ns ttdz tlu data clk to tri* * not fully tested, values based on design/characterization. 2.0 3.5 ns ttdv tlu data clk to driven* 1.5 3.5 ns table 54 signal groups in tlu timing diagrams signal group included signals control (t_ctl) ta18x - ta21x, tce0x - tce3x, twe0x - twe3x address (tan) ta0 - ta21 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
ac timing specifications 89 motorola general business information C5NPD0-DS/d rev 04 qmu timing specifications the qmu timing specifications are shown in figure 25 and described in table 55 . figure 25 qmu timing diagram data (tdn) td0 - td63 table 54 signal groups in tlu timing diagrams signal group included signals qclk cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 qcmdn (output) qdatan (output) qdatan (input) t qc t qdo t qdv t qdz t qds t qdh t qco table 55 qmu timing description symbol parameter min typ max unit comment tqc qmu cycle time 2 x tsc 4 x tsc ns ns 1x clock mode 2x clock mode tqco qmu ctrl output 1.5 1/2 tsc + 1.0 tsc + 1.0 ns 1x clock mode 2x clock mode tqds qmu data setup 3.1 ns tqdh qmu data hold 1.3 3.5 ns tqdo qmu data output 1.5 1/2 tsc + 1.0 tsc + 1.0 ns 1x clock mode 2x clock mode tqdz qmu data clk to tri* 1.1 5.5 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
90 chapter 3: electrical specifications C5NPD0-DS/d rev 04 motorola general business information tqdv qmu data clk to driven* 0.6 5.5 ns * not fully tested, values based on design/characterization. table 56 signal groups in qmu timing diagrams signal group included signals qcmdn qcmd0 - qcmd15, qsflow, qxctrl0, qxctrl1, qxrqst qdatan qdata0 - qdata31, qdpar table 55 qmu timing description (continued) (continued) symbol parameter min typ max unit comment f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola general business information C5NPD0-DS/d rev 04 C5NPD0-DS/d rev 04 chapter 4 mechanical specifications package views the c-5 network processor is an 838 pin (29 pins x 29 pins) ball grid array (bga) package as shown in the following illustrations. table 57 defines the package measurements. figure 26 c-5 network processor bga package side view hitce: green ceramic is thermally matched to fr4 circuit board. the aluminum lid is electrically connected to the grounded substrate of the c-5 np. neither the lid nor any heat sink connected to the lid should be part of a current-carrying path. it is acceptable, however, to connect the lid or heatsink to ground if necessary (through the standoff screws for the heat sink). a seating plane a 1 a 2 a 3 a 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
94 chapter 4: mechanical specifications C5NPD0-DS/d rev 04 motorola general business information figure 27 c-5 network processor bga package (bottom view) package measurements table 57 defines the c-5 np package measurements, providing nominal, minimum, and maximum sizes where appropriate. e b e d e d 1 e 1 ac ab aa z y x w v u t s r q p o n m l k j i h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2 5 26 27 28 29 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
marking codes 95 motorola general business information C5NPD0-DS/d rev 04 marking codes table 58 explains the marking on the c-5 np. reflow typical reflow profile for the c-5 switch module 1 follow the guidelines recommended by your solder paste supplier. flux requrements must be met for best solderability. 2 the temperature profile should be carefully characterized to ensure uniform temperature across the board and package. solder ball voiding may be affected by ramp rates and dwell times below and above liquidus. table 57 package measurements (reference figure 26 and figure 27 for symbols) symbol definition nom. (mm) min. (mm) max. (mm) a overall 5.63 5.31 5.95 a 1 ball height 0.89 a 2 c4 and die 0.88 a 3 body thickness 2.26 2.07 2.53 a 4 lid thickness 1.6 d body size 37.50 d 1 ball footprint (x) 35.56 e body size 37.50 e 1 ball footprint (y) 35.56 e ball pitch 1.27 b ball diameter 0.89 table 58 c-5 network processor marking codes marking (explanation of codes) top logo/part#/country of origin/date code bottom n/a pin 1 marking chamfered corner f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
96 chapter 4: mechanical specifications C5NPD0-DS/d rev 04 motorola general business information 3 a nitrogen atmosphere is not required, but will make the process more robust. it can make a difference for marginally solderable pc board pads. 4 full convection forced air furnaces work best, but ir, convection/ir, or vapor phase can be used. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola general business information C5NPD0-DS/d rev 04 C5NPD0-DS/d rev 04 index symbols 10/100 ethernet (rmii) configuration 32 10/100 ethernet signals 32 10/100 ethernet timing description 77 10/100 ethernet timing diagram 77 10/100 ethernet timing specifications 76 a about this guide 13 absolute maximum ratings 67 ac timing specifications 72 b block diagram, c-5 network processor 21 bmu sdram interface signals 47 bmu signal groups 89 bmu timing description 89 bmu timing diagram 89 bmu timing specifications 88 boundary scan cell types 63 boundary scan description language 66 bringup clock timing diagram 70 buffer management unit 24 c c-5 network processor absolute maximum ratings 67 c-5 network processor bga package, bottom view 94 c-5 network processor bga package, side view 93 c-5 network processor capacitance data 69 c-5 network processor dc characteristics 68 c-5 network processor power and thermal characteristics 70 c-5 np channel processors 22 channel processor interface signals 30 channel processors 22 channel processors physical interface signals and pins grouped by clusters 31 clock and reference signals 29 clock signals 29 clock timing specifications 73 configuration 10/100 ethernet (rmii) 32 ds1/t1 framer interface 32 fibrechannel tbi 35 gigabit ethernet 35 gigabit ethernet (gmii) 33 sonet oc-12 transceiver interface 37 sonet oc-3 transceiver interface 37 configurations gmii/tbi transmit and receive pin 34 connections power and ground (bottom view) 52 cp timing specifications 75 d data registers jtag 63 data sheet description and organization 13 dc characteristics 68 description functional 19 description language boundary scan 66 descriptions signal 27 diagram 10/100 ethernet timing 77 bmu timing 89 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
98 index C5NPD0-DS/d rev 04 motorola general business information bringup clock timing 70 ds1/ds3 ethernet timing 76 fabric processor timing 87 gigabit ethernet (tbi) timing 78 low speed serial interface timing 85 mdio serial interface timing 84 oc-3 timing 80 pci timing 82 pinout 27 prom interface 42 prom interface timing 86 qmu timing 91 signal groups in bmu timing 89 signal groups in qmu timing 92 signal groups in tlu timing 90 system clock timing 74 tlu timing 90 diagram, block c-5 network processor 21 ds1/ds3 ethernet timing description 76 ds1/ds3 ethernet timing diagram 76 ds1/ds3 timing specifications 75 ds1/t1 framer interface configuration 32 ds1/t1 framer interface signals 32 e electrical specifications 67 absolute maximum ratings 67 executive processor 22 pci 23 prom interface 23 serial bus interface 23 system interface signals 39 system interfaces 23 executive processor timing specifications 82 f fabric interface pin mapping power x mode 47 prizma mode 46 utopia2/utopia3 atm mode 45 utopia2/utopia3 phy mode 45 fabric processor 24 fabric processor interface signals 44 fabric processor timing description 87 fabric processor timing diagram 87 fabric processor timing specifications 86 functional description 19 g general system interface signal 43 gigabit ethernet (gmii) configuration 33 gigabit ethernet (gmii) signals one cluster example 34 gigabit ethernet (tbi) timing description 79 , 79 gigabit ethernet (tbi) timing diagram 78 gigabit ethernet and fibrechannel tbi configuration 35 gigabit ethernet and fibrechannel tbi signals example 36 gigabit gmii ethernet, tbi and mii interface timing specification 77 gmii/tbi transmit and receive pin configurations 34 guide conventions 14 i idcode register 64 instruction register instructions 65 j jtag data registers 63 jtag identification code and its sub-components 65 jtag instruction register 65 jtag internal register descriptions 63 jtag support pinouts 63 l low speed serial interface timing description 85 low speed serial interface timing diagram 85 low speed serial interface timing specifications 84 lvpecl specifications 29 lvttl specifications 29 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
index 99 motorola general business information C5NPD0-DS/d rev 04 m mdio serial interface timing description 84 mdio serial interface timing diagram 84 mdio serial interface timing specifications 83 measurements c-5 network processor 94 mechanical specifications 93 miscellaneous test signals for jtag, scan, and internal test routines 53 n no connection pins 53 o oc-12 signals 38 oc-12 timing description 81 oc-12 timing specifications 81 oc-3 signals 37 oc-3 timing description 80 oc-3 timing diagram 80 oc-3 timing specifications 79 operating conditions, recommended 67 p package measurements 94 pci signals 39 pci timing description 83 pci timing diagram 82 pci timing specifications 82 pin descriptions grouped by function 28 pin locations 28 pin number signals groups 53 pinout diagram 27 power and ground connections (bottom view) 52 power sequencing 69 , 70 power supply signals 50 power x mode, fabric interface pin mapping 47 prizma mode, c-5 network processor to fabric interface pin mapping 46 processor, executive 22 processor, fabric 24 prom interface diagram 42 prom interface signals 41 prom interface timing description 86 prom interface timing diagram 86 prom interface timing outline 43 prom interface timing specifications 85 q qmu signal groups 92 qmu sram interface signals 50 qmu timing description 91 qmu timing diagram 91 qmu timing specifications 91 queue management unit 25 r recommended operating conditions 67 register idcode 64 jtag instruction 65 related product documentation 17 revision history, for this guide 15 s serial interface signals 40 serial port signals 41 signal general system interface 43 signal descriptions 27 signal summary 27 signals 10/100 ethernet 32 bmu sdram interface 47 channel processor interface 30 clock 29 clock and reference 29 ds1/t1 framer interface 32 fabric processor interface 44 grouped by pin number 53 oc-12 38 oc-3 37 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
100 index C5NPD0-DS/d rev 04 motorola general business information pci 39 power supply 50 prom interface 41 qmu sram interface 50 serial interface 40 serial port 41 test 52 tlu sram interface 49 sonet oc-12 transceiver interface configuration 37 sonet oc-3 transceiver interface configuration 37 specifications 10/100 ethernet timing 76 ac timing 72 bmu timing 88 clock timing 73 cp timing 75 ds1/ds3 timing 75 electrical 67 executive processor timing 82 fabric processor timing 86 gigabit gmii ethernet, tbi and mii interface timing specification 77 low speed serial interface timing 84 mdio serial interface timing 83 mechanical 93 oc-12 timing 81 oc-3 timing 79 pci timing 82 prom interface timing 85 qmu timing 91 tlu timing 90 xp timing 82 system clock timing description 74 system clock timing diagram 74 system interfaces executive processor 23 t table lookup unit 25 test signals 52 test signals, miscellaneous, for jtag, scan, and internal test routines 53 thermal performance for c-5 network processor heat sink 72 timing outline prom interface 43 tlu signal groups 90 tlu sram interface signals 49 tlu timing description 90 tlu timing diagram 90 tlu timing specifications 90 transceiver interface configuration sonet oc-12 37 sonet oc-3 37 transmit and receive pin combinations for gigabit ethernet and fibrechannel 33 u using c-port electronic documents 13 utopia2/utopia3 atm mode, c-5 network processor to fabric interface pin mapping 45 utopia2/utopia3 phy mode, c-5 network processor to fabric interface pin mapping 45 x xp timing specifications 82 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola, inc . c-port family of network processors 120 water street, no. andover, ma 01845 voice: (978) 773-2300 fax: (978) 773-2301 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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